UM10503
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User manual
Rev. 2.1 — 10 December 2015
828 of 1441
NXP Semiconductors
UM10503
Chapter 28: LPC43xx/LPC43Sxx Ethernet
If the corresponding bit value of the register is 1, the frame is accepted. Otherwise, it is
rejected. If the PM (Pass All Multicast) bit is set in the MAC_CONFIG register, then all
multicast frames are accepted regardless of the multicast hash values.
If the Hash Table register is configured to be double-synchronized to the MII clock domain,
the synchronization is triggered only when Bits[31:24] (in Little-Endian mode) or Bits[7:0]
(in Big-Endian mode) of the Hash Table High/Low registers are written to. Please note that
consecutive writes to these register should be performed only after at least 4 clock cycles
in the destination clock domain when double synchronization is enabled.
The Hash Table High register contains the higher 32 bits of the Hash table.
See
for examples of how to configure the hash filter.
28.6.4 MAC Hash table low register
The Hash Table Low register contains the lower 32 bits of the Hash table.
See
for examples of how to configure the hash filter.
28.6.5 MAC MII Address register
The MII Address register controls the management cycles to the external PHY through the
management interface.
Table 604. MAC Hash table high register (MAC_HASHTABLE_HIGH, address 0x4001 0008) bit
description
Bit
Symbol
Description
Reset
value
Access
31:0
HTH
Hash table high
This field contains the upper 32 bits of Hash table.
0
R/W
Table 605. MAC Hash table low register (MAC_HASHTABLE_LOW, address 0x4001 0008) bit
description
Bit
Symbol
Description
Reset
value
Access
31:0
HTL
Hash table low
This field contains the upper 32 bits of Hash table.
0
R/W
