UM10503
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User manual
Rev. 2.1 — 10 December 2015
559 of 1441
NXP Semiconductors
UM10503
Chapter 22: LPC43xx/LPC43Sxx SD/MMC interface
22.6.20 FIFO Threshold Watermark Register
Table 377. FIFO Threshold Watermark Register (FIFOTH, address 0x4000 404C) bit description
Bit
Symbol
Value
Description
Reset
value
11:0
TX_WMARK
FIFO threshold watermark level when transmitting data to card. When
FIFO data count is less than or equal to this number, DMA/FIFO
request is raised. If Interrupt is enabled, then interrupt occurs. During
end of packet, request or interrupt is generated, regardless of
threshold programming. In non-DMA mode, when transmit FIFO
threshold (TXDR) interrupt is enabled, then interrupt is generated
instead of DMA request. During end of packet, on last interrupt, host is
responsible for filling FIFO with only required remaining bytes (not
before FIFO is full or after CIU completes data transfers, because
FIFO may not be empty). In DMA mode, at end of packet, if last
transfer is less than burst size, DMA controller does single cycles until
required bytes are transferred. 12 bits - 1 bit less than FIFO-count of
status register, which is 13 bits. Limitation: TX_WMark >= 1;
Recommended value: TX_WMARK = 16; (means less than or equal to
FIFO_DEPTH/2).
0
15:12
-
Reserved.
0
27:16
RX_WMARK
FIFO threshold watermark level when receiving data to card. When
FIFO data count reaches greater than this number, DMA/FIFO
request is raised. During end of packet, request is generated
regardless of threshold programming in order to complete any
remaining data. In non-DMA mode, when receiver FIFO threshold
(RXDR) interrupt is enabled, then interrupt is generated instead of
DMA request. During end of packet, interrupt is not generated if
threshold programming is larger than any remaining data. It is
responsibility of host to read remaining bytes on seeing Data Transfer
Done interrupt. In DMA mode, at end of packet, even if remaining
bytes are less than threshold, DMA request does single transfers to
flush out any remaining bytes before Data Transfer Done interrupt is
set. 12 bits - 1 bit less than FIFO-count of status register, which is 13
bits. Limitation: RX_WMark less than FIFO_DEPTH-2
Recommended: RX_WMARK = 15; (means greater than
(FIFO_DEPTH/2) - 1)
NOTE: In DMA mode during CCS time-out, the DMA does not
generate the request at the end of packet, even if remaining bytes are
less than threshold. In this case, there will be some data left in the
FIFO. It is the responsibility of the application to reset the FIFO after
the CCS time-out.
0x1F
