UM10503
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2015. All rights reserved.
User manual
Rev. 2.1 — 10 December 2015
526 of 1441
NXP Semiconductors
UM10503
Chapter 21: LPC43xx/LPC43Sxx General Purpose DMA (GPDMA)
21.6.19.1 Protection and access information
AHB access information is provided to the source and/or destination peripherals when a
transfer occurs. The transfer information is provided by programming the DMA channel
(the PROT bits of the CONTROL Register, and the LOCK bit of the CONFIG Register).
These bits are programmed by software and can be used by peripherals.
21.6.20 Channel Configuration registers
The eight CONFIG Registers are read/write with the exception of bit[17] which is
read-only. Used these to configure the DMA channel. The registers are not updated when
a new LLI is requested.
31
I
Terminal count interrupt enable bit.
0
R/W
0
The terminal count interrupt is disabled.
1
The terminal count interrupt is enabled.
Table 350. DMA Channel Control registers (CONTROL[0:7], 0x4000 210C (CONTROL0) to 0x4000 21EC (CONTROL7))
bit description
…continued
Bit
Symbol
Value Description
Reset
value
Access
Table 351. DMA Channel Configuration registers (CONFIG[0:7], 0x4000 2110 (CONFIG0) to 0x4000 21F0 (CONFIG7))
bit description
Bit
Symbol
Value
Description
Reset
value
Access
0
E
Channel enable. Reading this bit indicates whether a channel is
currently enabled or disabled:
The Channel Enable bit status can also be found by reading the
ENBLDCHNS Register.
A channel can be disabled by clearing the Enable bit. This
causes the current AHB transfer (if one is in progress) to
complete and the channel is then disabled. Any data in the FIFO
of the relevant channel is lost. Restarting the channel by setting
the Channel Enable bit has unpredictable effects, the channel
must be fully re-initialized.
The channel is also disabled, and Channel Enable bit cleared,
when the last LLI is reached, the DMA transfer is completed, or
if a channel error is encountered.
If a channel must be disabled without losing data in the FIFO,
the Halt bit must be set so that further DMA requests are
ignored. The Active bit must then be polled until it reaches 0,
indicating that there is no data left in the FIFO. Finally, the
Channel Enable bit can be cleared.
Remark:
The GPDMA pre-loads the data from the source
memory as soon as the channel is enabled. The data
pre-loading occurs independently of receiving a DMA transfer
request.
0
R/W
0
Channel disabled.
1
Channel enabled.
