UM10503
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User manual
Rev. 2.1 — 10 December 2015
494 of 1441
NXP Semiconductors
UM10503
Chapter 20: LPC43xx/LPC43Sxx Serial GPIO (SGPIO)
20.6.27 Exchange clock interrupt status register
The STATUS_1 register bits are set when the shadow and data registers are exchanged.
The bits in this registers are set independently of the value of the corresponding
ENABLE_1 bits. The bits in this register can be read at any time but can only be changed
by writing to the corresponding bits in the SET_STATUS_1 or CLR_STATUS_1 registers.
20.6.28 Exchange clock interrupt clear status register
20.6.29 Exchange clock interrupt set status register
20.6.30 Pattern match interrupt clear mask register
20.6.31 Pattern match interrupt set mask register
Table 302. Exchange clock interrupt status register (STATUS_1, address 0x4010 1F2C) bit
description
Bit
Symbol
Description
Reset
value
Access
15:0
STATUS_CCI
Exchange clock interrupt status of slice n.
0
R
31:16 -
Reserved.
-
-
Table 303. Exchange clock interrupt clear status register (CLR_STATUS_1, address 0x4010
1F30) bit description
Bit
Symbol
Description
Reset
value
Access
15:0
CLR_STATUS_CCI
Exchange clock interrupt clear status of slice n. 0
W
31:16 -
Reserved.
-
-
Table 304. Exchange clock interrupt set status register (SET_STATUS_1, address 0x4010
1F34) bit description
Bit
Symbol
Description
Reset
value
Access
15:0
SET_STATUS_CCI
Exchange clock interrupt set status of slice n.
0
W
31:16 -
Reserved.
-
-
Table 305. Pattern match interrupt clear mask register (CLR_EN_2, address 0x4010 1F40) bit
description
Bit
Symbol
Description
Reset
value
Access
15:0
CLR_EN2_PMI
1 = Match interrupt clear mask of slice n.
0
W
31:16 -
Reserved.
-
-
Table 306. Pattern match interrupt set mask register (SET_EN_2, address 0x4010 1F44) bit
description
Bit
Symbol
Description
Reset
value
Access
15:0
SET_EN_PMI
1 = Match interrupt set mask of slice n.
0
W
31:16 -
Reserved.
-
-
