UM10503
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© NXP B.V. 2015. All rights reserved.
User manual
Rev. 2.1 — 10 December 2015
1293 of 1441
NXP Semiconductors
UM10503
Chapter 46: LPC43xx/LPC43Sxx I2C-bus interface
When the slave address and R/W bit have been transmitted and an acknowledgment bit
has been received, the SI bit is set again, and the possible status codes now are 0x18,
0x20, or 0x38 for the master mode, or 0x68, 0x78, or 0xB0 if the slave mode was enabled
(by setting AA to 1). The appropriate actions to be taken for each of these status codes
are shown in
to
.
46.8.2 Master Receiver mode
In the master receiver mode, data is received from a slave transmitter. The transfer is
initiated in the same way as in the master transmitter mode. When the START condition
has been transmitted, the interrupt service routine must load the slave address and the
data direction bit to the I
2
C Data register (DAT), and then clear the SI bit. In this case, the
data direction bit (R/W) should be 1 to indicate a read.
When the slave address and data direction bit have been transmitted and an
acknowledge bit has been received, the SI bit is set, and the Status Register will show the
status code. For master mode, the possible status codes are 0x40, 0x48, or 0x38. For
slave mode, the possible status codes are 0x68, 0x78, or 0xB0. For details, refer to
After a Repeated START condition, I
2
C may switch to the master transmitter mode.
Fig 172. Format in the Master Transmitter mode
A = Acknowledge (SDA low)
A = Not acknowledge (SDA high)
S = START condition
P = STOP condition
S
SLAVE ADDRESS
RW=0
A
DATA
A
A/A
P
from Master to Slave
from Slave to Master
DATA
n bytes data transmitted
Fig 173. Format of Master Receiver mode
DATA
A = Acknowledge (SDA low)
A = Not acknowledge (SDA high)
S = START condition
P = STOP condition
S
SLAVE ADDRESS
RW=1
A
DATA
P
n bytes data received
from Master to Slave
from Slave to Master
A
A
