UM10503
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User manual
Rev. 2.1 — 10 December 2015
1288 of 1441
NXP Semiconductors
UM10503
Chapter 46: LPC43xx/LPC43Sxx I2C-bus interface
46.7.6 I
2
C Control Clear register
The CONCLR registers control clearing of bits in the CON register that controls operation
of the I
2
C interface. Writing a one to a bit of this register causes the corresponding bit in
the I
2
C control register to be cleared. Writing a zero has no effect.
AAC
is the Assert Acknowledge Clear bit. Writing a 1 to this bit clears the AA bit in the
CONSET register. Writing 0 has no effect.
SIC
is the I
2
C Interrupt Clear bit. Writing a 1 to this bit clears the SI bit in the CONSET
register. Writing 0 has no effect.
STAC
is the START flag Clear bit. Writing a 1 to this bit clears the STA bit in the CONSET
register. Writing 0 has no effect.
I
2ENC
is the I
2
C Interface Disable bit. Writing a 1 to this bit clears the I2EN bit in the
CONSET register. Writing 0 has no effect.
46.7.7 I
2
C Monitor mode control register
This register controls the Monitor mode which allows the I
2
C module to monitor traffic on
the I
2
C bus without actually participating in traffic or interfering with the I
2
C bus.
Table 1092.I
2
C Control Clear register (CONCLR - address 0x400A 1018 (I2C0) and
0x400E 0018 (I2C1)) bit description
Bit
Symbol
Description
Reset
value
1:0
-
Reserved. User software should not write ones to reserved bits. The
value read from a reserved bit is not defined.
-
2
AAC
Assert acknowledge Clear bit.
3
SIC
I
2
C interrupt Clear bit.
0
4
-
Reserved. User software should not write ones to reserved bits. The
value read from a reserved bit is not defined.
-
5
STAC
START flag Clear bit.
0
6
I2ENC
I
2
C interface Disable bit.
0
7
-
Reserved. User software should not write ones to reserved bits. The
value read from a reserved bit is not defined.
-
31:8
-
Reserved. The value read from a reserved bit is not defined.
-
