UM10503
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User manual
Rev. 2.1 — 10 December 2015
1209 of 1441
NXP Semiconductors
UM10503
Chapter 44: LPC43xx/LPC43Sxx I2S interface
Remark:
The FIFOs contain eight 32 bit Dwords. Therefore, if the I
2
S controller is
configured for 32-bit mode (see
and
), the maximum allowed FIFO
level is 4.
44.6.7 I2S DMA Configuration Register 2
The DMA2 register controls the operation of DMA request 2. The function of bits in DMA2
are shown in
.
This register enables the DMA for the I
2
S receive and transmit channels and sets the
FIFO level.
Remark:
The FIFOs contain eight 32 bit Dwords. Therefore, if the I
2
S controller is
configured for 32-bit mode (see
and
), the maximum allowed FIFO
level is 4.
Table 1006.I2S DMA Configuration register 1 (DMA1, address 0x400A 2014 (I2S0) and 0x400A
3014 (I2S1)) bit description
Bit
Symbol
Description
Reset
value
0
RX_DMA1_ENABLE
When 1, enables DMA1 for I2S receive.
0
1
TX_DMA1_ENABLE
When 1, enables DMA1 for I2S transmit.
0
7:2
-
Reserved, user software should not write ones to
reserved bits. The value read from a reserved bit is not
defined.
0
11:8
RX_DEPTH_DMA1
Set the FIFO level that triggers a receive DMA request on
DMA1.
0
15:12
-
Reserved, user software should not write ones to
reserved bits. The value read from a reserved bit is not
defined.
-
19:16
TX_DEPTH_DMA1
Set the FIFO level that triggers a transmit DMA request
on DMA1.
0
31:20
-
Reserved, user software should not write ones to
reserved bits. The value read from a reserved bit is not
defined.
-
Table 1007.I2S DMA Configuration register 2 (DMA2, address 0x400A 2018 (I2S0) and 0x400A
3018 (I2S1)) bit description
Bit
Symbol
Description
Reset
value
0
RX_DMA2_ENABLE
When 1, enables DMA1 for I2S receive.
0
1
TX_DMA2_ENABLE
When 1, enables DMA1 for I2S transmit.
0
7:2
-
Reserved.
0
11:8
RX_DEPTH_DMA2
Set the FIFO level that triggers a receive DMA request
on DMA2.
0
