UM10503
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© NXP B.V. 2015. All rights reserved.
User manual
Rev. 2.1 — 10 December 2015
1128 of 1441
NXP Semiconductors
UM10503
Chapter 40: LPC43xx/LPC43Sxx USART0_2_3
40.6.6.1 DMA Operation
The user can optionally operate the USART transmit and/or receive using DMA. The DMA
mode is determined by the DMA Mode Select bit in the FCR register. Note that for DMA
operation as for any operation of the USART, the FIFOs must be enabled via the FIFO
Enable bit in the FCR register.
USART receiver DMA
In DMA mode, the receiver DMA request is asserted when the receiver FIFO level
becomes equal to or greater than trigger level, or if a character time-out occurs. See the
description of the RX Trigger Level above. The receiver DMA request is cleared by the
DMA controller.
USART transmitter DMA
In DMA mode, the transmitter DMA request is asserted when the transmitter FIFO
transitions to not full. The transmitter DMA request is cleared by the DMA controller.
40.6.7 USART Line Control Register
The LCR determines the format of the data character that is to be transmitted or received.
1
RXFIFORES
RX FIFO Reset.
0
0
No effect. No impact on either of USART FIFOs.
1
Clear. Writing a logic 1 to FCR[1] will clear all bytes in USART Rx FIFO, reset the
pointer logic. This bit is self-clearing.
2
TXFIFORES
TX FIFO Reset.
0
0
No effect. No impact on either of USART FIFOs.
1
Clear. Writing a logic 1 to FCR[2] will clear all bytes in USART TX FIFO, reset the
pointer logic. This bit is self-clearing.
3
DMAMODE
DMA Mode Select. When the FIFO enable bit (bit 0 of this register) is set, this bit
selects the DMA mode.
0
5:4
-
Reserved, user software should not write ones to reserved bits. The value read from
a reserved bit is not defined.
NA
7:6
RXTRIGLVL
RX Trigger Level.
These two bits determine how many receiver USART FIFO characters must be
written before an interrupt is activated.
0
0x0
Level 0. Trigger level 0 (1 character or 0x01).
0x1
Level 1. Trigger level 1 (4 characters or 0x04).
0x2
Level 2. Trigger level 2 (8 characters or 0x08).
0x3
Level 3. Trigger level 3 (14 characters or 0x0E).
31:8 -
-
Reserved
-
Table 932. USART FIFO Control Register Write Only (FCR, addresses 0x4008 1008 (USART0), 0x400C 1008
(USART2), 0x400C 2008 (USART3)) bit description
Bit
Symbol
Value
Description
Reset
value
