UM10503
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© NXP B.V. 2015. All rights reserved.
User manual
Rev. 2.1 — 10 December 2015
1119 of 1441
NXP Semiconductors
UM10503
Chapter 40: LPC43xx/LPC43Sxx USART0_2_3
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Smart Card interface.
40.4 General description
The architecture of the USART is shown below in the block diagram.
The APB interface provides a communications link between the CPU or host and the
USART.
The USART receiver block, RX, monitors the serial input line, RXD, for valid input. The
USART RX Shift Register (RSR) accepts valid characters via RXD. After a valid character
is assembled in the RSR, it is passed to the USART RX Buffer Register FIFO to await
access by the CPU or host via the generic host interface.
The USART transmitter block, TX, accepts data written by the CPU or host and buffers the
data in the USART TX Holding Register FIFO (THR). The USART TX Shift Register (TSR)
reads the data stored in the THR and assembles the data to transmit via the serial output
pin, TXD1.
The USART Baud Rate Generator block, BRG, generates the timing enables used by the
USART TX and RX blocks. The BRG clock input source is PCLK. The main clock is
divided down per the divisor specified in the DLL and DLM registers. This divided down
clock is a 16x oversample clock, NBAUDOUT.
The interrupt interface contains registers IER and IIR. The interrupt interface receives
several one clock wide enables from the TX and RX blocks.
Status information from the TX and RX is stored in the LSR. Control information for the TX
and RX is stored in the LCR.
