UM10503
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© NXP B.V. 2015. All rights reserved.
User manual
Rev. 2.1 — 10 December 2015
1110 of 1441
NXP Semiconductors
UM10503
Chapter 39: LPC43xx/LPC43Sxx Event monitor/recorder
39.5 General description
The Event Monitor/Recorder relies on VBAT to be present at all times. A loss or dip of
VBAT voltage causes the Real-Time Clock power fail detector to reset the event
recordings. It is therefore important to have a VBAT power source that can deliver power
for the longest expected mains power outage.
Once system power is restored, the CPU can check for recorded tamper events. If there
were tamper events, the timestamp registers for the first and the last event would indicate
the period over which they occurred.
An edge on an event input is sampled with either a 1 kHz clock, a 64 Hz clock, or a 16 Hz
clock. A transition in either direction must be captured by two successive edges of this
clock in order to be recognized as a valid transition. This provides a 1-2 ms rejection filter
in case of the 1 kHz sample clock, a 15.6-31.2 ms rejection filter in case of the 64 Hz
sample clock, and a 62.5-125ms rejection filter in case of the 16 Hz sample clock. Such
an event will set the EVx bit in the ERSTATUS register on the next rising edge of the 1 Hz
clock.
If an event occurs, a timestamp will be taken from the RTC and stored in the
ERLASTSTAMPx register. This timestamp will be updated with every new event. The
event will also update the ERFIRSTSTAMPx register if this is the first event to occur since
the last time the EVx bit in the status register was cleared.
In addition to taking the timestamp(s), a 3-bit counter (ERCOUNTERx) will be
incremented on the rising edge of the 1 Hz clock (i.e. coincident with the ERLASTSTAMPx
register being updated). The counter stops counting and holds when it reaches a count of
seven. It will be cleared automatically when the software clears the EVx bit in the status
register.
An event can be enabled to clear the backup registers in the RTC block asynchronously.
This works even when the 32 kHz oscillator is not running or when Event
Monitor/Recorder clocks are disabled.
The following figure shows a block diagram of the Event Monitor/Recorder.
