UM10503
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© NXP B.V. 2015. All rights reserved.
User manual
Rev. 2.1 — 10 December 2015
1014 of 1441
NXP Semiconductors
UM10503
Chapter 31: LPC43xx/LPC43Sxx State Configurable Timer (SCT) with
This application of the SCT uses the following configuration (all register values not listed
in
are set to their default values):
Fig 107. SCT configuration example
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Table 779. SCT configuration example
Configuration
Registers
Setting
Counter
CONFIG
Uses one counter (UNIFY = 1).
CONFIG
Enable the autolimit for MAT0. (AUTOLIMIT = 1.)
CTRL
Uses unidirectional counter (BIDIR_L = 0).
Clock base
CONFIG
Uses default values for clock configuration.
Match/Capture registers
REGMODE
Configure one match register for each match event by setting
REGMODE_L bits 0,1, 2, 3, 4 to 0. This is the default.
Define match values
MATCH0/1/2/3/4
Set a match value MATCH0/1/2/3/4_L in each register. The match 0
register serves as an automatic limit event that resets the counter.
without using an event. To enable the automatic limit, set the
AUTOLIMIT bit in the CONFIG register.
Define match reload
values
MATCHREL0/1/2/3/4
Set a match reload value RELOAD0/1/2/3/4_L in each register
(same as the match value in this example).
Define when event 0
occurs
EVCTRL0
•
Set COMBMODE = 0x1. Event 0 uses match condition only.
•
Set MATCHSEL = 1. Select match value of match register 1.
The match value of MAT1 is associated with event 0.
Define when event 1
occurs
EVCTRL1
•
Set COMBMODE = 0x1. Event 1 uses match condition only.
•
Set MATCHSEL = 2 Select match value of match register 2. The
match value of MAT2 is associated with event 1.
