NXP Semiconductors LPC29 Series User Manual Download | Manualshive

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UM10316_0

© NXP B.V. 2008. All rights reserved.

User manual

Rev. 00.06 — 17 December 2008

372 of 571

NXP Semiconductors

UM10316

Chapter 22: LPC29xx LIN 0/1

Table 309. LIN master-controller interrupt and capture register bit description

* = reset value

Bit

Symbol

Access

Value

Description

31 to 12 reserved

R

-

Reserved; read as logic 0

11 to 8

EC[3:0]

R

Error capture

0000*

Bit error in sync-break field

0001

Bit error in sync field

0010

Bit error in identifier field

0011

Bit error in data field

0100

Bit error in checksum field

0101

Bit error in inter-byte space

0110

Bit error in stop bit of received slave responses

0111

Reserved

1000

Recessive line-clamped error. RXD / TXD line
stuck recessive

1001

Dominant line-clamped error. RXD / TXD line
stuck dominant

1010

Reserved

:

:

1111

Reserved

7

reserved

R

-

Reserved; read as logic 0

6

WPI

R

Wake-up and LIN protocol-error interrupt

1

A dominant bus level has been detected when
the LIN bus was idle. A dominant level on the
LIN bus can be caused by a wake-up message
from a slave node, or by arbitrarily created or
faulty messages generated by LIN slaves, or by
a stuck dominant level

0*

5

RTLCEI

R

Line-clamped error interrupt

1

No valid message can be generated on the LIN
bus due to a clamped dominant or recessive
RXD or TXD line

0*

4

NRI

R

Slave-not-responding error interrupt

1

The slave response was not completed within a
certain time-out period. The time-out period is
configurable via the time-out register

0*

3

CSI

R

Checksum-error interrupt

1

The received checksum field does not match
the calculated checksum

0*

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Summary of Contents for LPC29 Series

Page 1: ...microcontroller with CAN and LIN Rev 00 06 17 December 2008 User manual Document information Info Content Keywords LPC2917 01 LPC2919 01 LPC2927 LPC2929 LPC2921 LPC2923 LPC2925 LPC2930 LPC2939 User Ma...

Page 2: ...iption of CGU1 and internal base clocks SCU chapter description of SFSP_5_18 18 SEC_DIS and SEC_STA registers added RGU chapter updated PMU chapter updated CFID chapter added Flash EEPROM chapter upda...

Page 3: ...le 1 2 3 General features Remark See Table 1 2 for feature details for each LPC29xx part ARM968E S processor running at frequencies of up to 125 MHz maximum Multi layer AHB system bus at 125 MHz with...

Page 4: ...re encoder 32 bit watchdog with timer change protection running on safe clock Up to 108 general purpose I O pins with programmable pull up pull down or bus keeper Vectored Interrupt Controller VIC wit...

Page 5: ...lastic low profile quad flat package 144 leads body 20 20 1 4 mm SOT486 1 LPC2919FBD144 01 LQFP144 plastic low profile quad flat package 144 leads body 20 20 1 4 mm SOT486 1 LPC2921FBD100 LQFP100 plas...

Page 6: ...7 19 devices Table 2 LPC29xx part overview Part number Flash SRAM incl ETB TCM I D CAN LIN UART Pins UART RS485 SPI 3V3 ADC 5 V ADC SMC USB device USB host USB OTG ETM QEI I2C bus Clkout pin LPC2939 7...

Page 7: ...slave slave slave slave slave slave slave EXTERNAL STATIC MEMORY CONTROLLER GPDMA CONTROLLER GPDMA REGISTERS EMBEDDED FLASH 512 768 kB 16 kB EEPROM EMBEDDED SRAM 32 kB SYSTEM CONTROL TIMER0 1 MTMR CA...

Page 8: ...GISTERS EMBEDDED FLASH 512 256 128 kB 16 kB EEPROM EMBEDDED SRAM 16 kB LPC2925 only SYSTEM CONTROL TIMER0 1 MTMR CAN0 1 GLOBAL ACCEPTANCE FILTER PWM0 1 2 3 3 3 V ADC1 2 EVENT ROUTER EMBEDDED SRAM 16 k...

Page 9: ...GPDMA REGISTERS EMBEDDED FLASH 512 768 kB 16 kB EEPROM EMBEDDED SRAM 32 kB SYSTEM CONTROL TIMER0 1 MTMR CAN0 1 GLOBAL ACCEPTANCE FILTER UART LIN0 1 PWM0 1 2 3 3 3 V ADC1 2 EVENT ROUTER EMBEDDED SRAM...

Page 10: ...LLER GPDMA CONTROLLER GPDMA REGISTERS EMBEDDED SRAM 32 kB SYSTEM CONTROL TIMER0 1 MTMR CAN0 1 GLOBAL ACCEPTANCE FILTER UART LIN0 1 PWM0 1 2 3 3 3 V ADC1 2 EVENT ROUTER EMBEDDED SRAM 16 kB GENERAL PURP...

Page 11: ...GPDMA REGISTERS EMBEDDED FLASH 768 kB 16 kB EEPROM EMBEDDED SRAM 32 kB SYSTEM CONTROL TIMER0 1 MTMR CAN0 1 GLOBAL ACCEPTANCE FILTER UART LIN0 1 PWM0 1 2 3 3 3 V ADC1 2 EVENT ROUTER EMBEDDED SRAM 16 k...

Page 12: ...MI S 32 bit RISC processor SMC Static Memory Controller For external static memory banks SRAM Internal Static Memory Clock domain Flash Flash Internal Flash Memory FMC Flash Memory Controller Controll...

Page 13: ...a write ahead buffer one transaction deep This implies that when the ARM968E S issues a buffered write action to a register located on the APB side of the bridge it continues even though the actual w...

Page 14: ...te back cycles The ARM968E S processor also employs a unique architectural strategy known as THUMB which makes it ideally suited to high volume applications with memory restrictions or to applications...

Page 15: ...SRAM TCM I D SMC SRAM 16 kB SRAM 32 kB ETB 8KB LPC2917 01 512 kB yes yes yes 16 16 kB 8 banks 16 MB each LPC2919 01 768 kB yes yes yes 16 16 kB 8 banks 16 MB each LPC2921 128 kB yes no yes 16 16 kB L...

Page 16: ...ions The ARM9 processor has a 4 GB of address space The LPC29xx has divided this memory space into eight regions of 512 MB each Each region is used for a dedicated purpose An exception to this is regi...

Page 17: ...heral subsystem 2 peripheral subsystem 4 peripheral subsystem 6 0xE018 2000 0xE018 0000 32 kB AHB SRAM 1 16 kB AHB SRAM 1 reserved USB controller 1 DMA controller 8 kB ETB SRAM ETB control reserved IT...

Page 18: ...made for region 0 When enabled the Tightly Coupled Memories TCMs occupy fixed address locations in region 0 as indicated in Figure 2 6 Information on how to enable the TCMs can be found in the ARM do...

Page 19: ...he embedded flash A data area of 2 Mbyte to be prepared for a larger flash memory instance and a configuration area of 4 kB are reserved for each embedded flash instance Although the LPC29xx contains...

Page 20: ...ontroller VIC The PCRSS is a DTL cluster in which the CGU PMU and RGU are connected to the AHB system bus via an AHB2DTL adapter The VIC is a DTL target connected to the AHB system bus via its own AHB...

Page 21: ...0000 0008h Software interrupt 0000 000Ch Pre fetch abort instruction fetch memory fault 0000 0010h Data abort data access memory fault 0000 0014h reserved 0000 0018h IRQ 0000 001Ch FIQ Table 9 Periphe...

Page 22: ...7000h CANAFR RegBase CAN acceptance filter registers E008 8000h CANCS RegBase CAN central status registers E008 9000h LIN RegBase LIN master controller 0 E008 A000h LIN RegBase LIN master controller...

Page 23: ...all subsystems A second dedicated CGU1 provides the clocks for the USB block and a clock output The CGU1 has two clock inputs to its PLL which are internally connected to two base clocks in the CGU0 B...

Page 24: ...varies for different LPC29xx parts Fig 9 LPC29xx clock generation TIMER0 1 MTMR PWM0 1 2 3 ADC0 1 2 QEI modulation and sampling control subsystem BASE_MSCSS_CLK branch clocks branch clocks BASE_ADC_C...

Page 25: ...Name Frequency MHz 1 Description 0 BASE_SAFE_CLK 0 4 base safe clock always on for WDT 1 BASE_SYS_CLK 125 base system clock ARM and AHB clock 2 BASE_PCR_CLK 0 4 2 base PCR subsystem clock for power c...

Page 26: ...t is shown in Figure 3 11 Fig 10 Schematic representation of the CGU0 400 kHz LP_OSC PLL FDIV0 EXTERNAL OSCLLLATOR FDIV1 FDIV6 OUT 0 OUT 1 OUT 11 clkout clkout120 clkout240 CLOCK GENERATION UNIT CGU0...

Page 27: ...tor control register Even when enabled this can be bypassed using the BYPASS field in the same register In this case the input of the OSC1M crystal is fed directly to the output The XO50M oscillator h...

Page 28: ...e feedback divider is 1 In normal mode the post divider is enabled and the following relations are verified Fclkout MDIV Fclkin Fcco 2 PDIV Values of the dividers are chosen with the following process...

Page 29: ...domains These settings are controlled by the PD and AUTOBLOK fields respectively The clock output can trigger disabling of the clock branch on a specific polarity of the output This is controlled via...

Page 30: ...sequence for programing a complete clock path 4 CGU1 functional description The CGU1 block is functionally identical to the CGU0 block and generates two clocks for the USB interface and a dedicated ou...

Page 31: ...on board peripherals such as the UARTs SPI Watchdog timers CAN controller LIN master controller ADCs and flash memory interface Fig 14 Block diagram of the CGU1 PLL FDIV0 OUT 0 OUT 2 clkout clkout120...

Page 32: ...IV_STATUS_4 FDIV 4 frequency divider status register see Table 3 21 050h R W 0000 1001h FDIV_CONF_4 FDIV 4 frequency divider control register see Table 3 22 054h R 0000 1001h FDIV_STATUS_5 FDIV 5 freq...

Page 33: ...CLK see Table 3 26 0ACh R 0000 0000h ADC_CLK_STATUS Output clock status register for BASE_ADC_CLK see Table 3 25 0B0h R W 0000 0000h ADC_CLK_CONF Output clock configuration register for BASE_ADC_CLK s...

Page 34: ...affected by several factors Quantization error is noticeable if the ratio between the two clocks is large e g 100 kHz vs 1kHz because one counter saturates while the other still has only a small count...

Page 35: ...has only one fractional divider register 5 2 Clock detection register Each clock generator has a clock detector associated with it to alert the system if a clock is removed or connected The status re...

Page 36: ...Bit Symbol Access Value Description 31 to 12 reserved R Reserved 11 FDIV6_PRESENT R Activity detection register for FDIV 6 CGU0 only 1 Clock present 0 Clock not present 10 FDIV5_PRESENT R Activity det...

Page 37: ...ot present 1 XTAL_PRESENT CGU0 or BASE_ICLK0_CLK_ PRESENT CGU1 R Activity detection register for crystal oscillator output 1 Clock present 0 Clock not present 0 LP_OSC_PRESEN T CGU0 or BASE_ICLK1_CLK_...

Page 38: ...can be inputs to the PLL Post divider ratio programming The division ratio of the post divider is controlled by PSEL 0 1 in the PLL_CONTROL register The division ratio is twice the value of P This gua...

Page 39: ...te values for M and P 1 Specify the input clock frequency fclkin 2 Calculate M to obtain the desired output frequency fclkout PLL with M fclkout fclkin 3 Find a value for P so that fcco 2 P fclkout 4...

Page 40: ...ator CGU0 or BASE_ICLK1_CLK CGU1 02h to FFh Not used 23 to 16 MSEL 4 0 R W Feedback divider division ratio M 1 00000 1 00001 2 00010 3 00011 4 00100 5 11111 32 15 to 12 reserved R Reserved 11 AUTOBLOK...

Page 41: ...register FDIV_CONF_n for each frequency divider n 0 6 The frequency divider divides the incoming clock by LOAD DENOMINATOR where LOAD and DENOMINATOR are both 12 bit values programmed in the control r...

Page 42: ...guration register for each CGU output clock generated All output generators have the same register bits An exception is the output generators for BASE_SAFE_CLK and BASE_PCR_CLK which are described her...

Page 43: ...l block The integer divider has a 3 bit control signal IDIV and divides the incoming clock by any value from 1 through 8 The divider value is equal to IDIV 1 if IDIV is equal to zero the incoming cloc...

Page 44: ...xFFFF 8088 UART address 0xFFFF 8098 SPI address 0xFFFF 80A0 TMR address 0xFFFF 80A8 ADC address 0xFFFF 80B0 reset value Bit Symbol Access Value Description 31 to 24 CLK_SEL R W selected source clock 0...

Page 45: ...8 The divider value is equal to IDIV 1 if IDIV is equal to zero the incoming clock is passed on directly to the next stage When the input to the integer divider has a 50 duty cycle the divided output...

Page 46: ...0xFFFF 8FF4 CGU0 and 0xFFFF BFF4 CGU1 reset value Bit Symbol Access Value Description 31 to 1 reserved R Reserved do not modify Read as logic 0 write as logic 0 0 RRBUS R W Bus write disable bit 1 No...

Page 47: ...le LP_OSC source for RGU_RST RGU_RST POR_RST RST_N pin RGU internal source for PCR_RST PCR_RST RGU_RST WATCHDOG PCR Power Clock and Reset internal source for COLD_RST COLD_RST PCR_RST parts with COLD_...

Page 48: ...ses depend on the reset hierarchy POR reset does not have a reset source register as it can only be activated by POR RGU reset Watchdog reset PCR Power control Clock and Reset Subsystem reset Cold res...

Page 49: ...see Table 4 36 114h R W tbd RESET_STATUS1 Reset status register 1 see Table 4 37 118h R W tbd RESET_STATUS2 Reset status register 2 see Table 4 38 11Ch R W tbd RESET_STATUS3 Reset status register 3 se...

Page 50: ...8h R W 0000 0040h MSCSS_PWM_RST_SRC Source register for MSCSS PWM reset see Table 4 46 4CCh R W 0000 0040h MSCSS_ADC_RST_SRC Source register for MSCSS ADC reset see Table 4 46 4D0h R W 0000 0040h MSCS...

Page 51: ...L W Activate AHB_RST 28 VIC_RST_CTRL W Activate VIC_RST 27 to 25 reserved R Reserved do not modify Write as logic 0 24 USB W Activate USB_RST 23 DMA_RST_CTRL W Activate DMA_RST 22 MSCSS_QEI_RST_CTRL W...

Page 52: ...e RGU 10 Reserved 11 Reset control register 7 and 6 COLD_RST_STAT R W Status of cold reset 00 No reset activated since RGU last came out of reset 01 Input reset to the RGU 10 Reserved 11 Reset control...

Page 53: ...l register 29 and 28 IVNSS_A2V_RST_STAT R W Reset IVNSS AHB2APB status 00 No reset activated since RGU last came out of reset 01 Input reset to the RGU 10 Reserved 11 Reset control register 27 and 26...

Page 54: ...ster 15 and 14 reserved R Reserved do not modify Read as logic 0 write as logic 0 13 and 12 SMC_RST_STAT R W Reset SMC status 00 No reset activated since RGU last came out of reset 01 Input reset to t...

Page 55: ...do not modify Read as logic 0 27 and 26 AHB_RST_STAT R W Reset AHB status 00 No reset activated since RGU last came out of reset 01 Input reset to the RGU 10 Reserved 11 Reset control register 25 and...

Page 56: ...ved 11 Reset control register 9 and 8 MSCSS_TMR_RST_STAT R W Reset MSCSS Timer status 00 No reset activated since RGU last came out of reset 01 Input reset to the RGU 10 Reserved 11 Reset control regi...

Page 57: ...5 reserved R Reserved do not modify 4 WARM_RST_STAT R 1 Current state of WARM_RST 3 COLD_RST_STAT R 1 Current state of COLD_RST 2 PCR_RST_STAT R 1 Current state of PCR_RST 1 RGU_RST_STAT R 1 Current...

Page 58: ...f the RGU which is activated by the Watchdog Timer or the RGU reset see Table 10 92 To be able to detect the source of the next PCR reset the register should be cleared by writing a 1 after read 13 SP...

Page 59: ...xt reset the register should be cleared by writing a 0 after read Table 43 PCR_RST_SRC register bit description PCR_RST_SRC address 0xFFFF 9408 reset value Bit Symbol Access Value Description 31 to 4...

Page 60: ...conductors UM10316 Chapter 4 LPC29xx Reset Generation Unit RGU 4 5 RGU bus disable register The BUS_DISABLE register prevents any register in the CGU from being written to Table 47 BUS_DISABLE registe...

Page 61: ...ecember 2008 User manual Table 48 Branch clocks implemented in LPC29xx x CLK_CFG_ or CLK_STAT_ Part SRAM Flash USB GPIO ADC xRAM0 xRAM1 xFMC xUSB_CLK xUSB_ I2C_CLK xUSB xGPIO xADC0 xADC0_ APB xADC1 xA...

Page 62: ...YS_IVNSS_A CLK_SYS_MSCSS_A CLK_SYS_GPIO4 CLK_SYS_GPIO5 CLK_SYS_DMA CLK_SYS_USB BASE_PCR_CLK CLK_PCR_SLOW 1 BASE_IVNSS_CLK CLK_IVNSS_APB CLK_IVNSS_CANCA CLK_IVNSS_CANC0 CLK_IVNSS_CANC1 CLK_IVNSS_I2C0 C...

Page 63: ...ia the corresponding registers CLK_CFG_ leaf The following clock leaves are exceptions to the general rule CLK_SYS_CPU cannot be disabled CLK_SYS cannot be disabled CLK_SYS_PCR cannot be disabled BASE...

Page 64: ...ister BASE_STAT and contains one bit per clock branch 4 PMU register overview The PMU registers have an offset to the base address PMU RegBase which can be found in the memory map see Section 2 2 Tabl...

Page 65: ...AT_PESS AHB APB clock to PeSS module status register see Table 5 54 250h R W 0000 0001h CLK_CFG_GPIO0 APB clock to General Purpose I O 0 configuration register see Table 5 53 254h R 0000 0001h CLK_STA...

Page 66: ...B clock to IVNSS module status register see Table 5 54 408h R W 0000 0001h CLK_CFG_CANCA IP clock to CAN gateway acceptance filter configuration register see Table 5 53 40Ch R 0000 0001h CLK_STAT_CANC...

Page 67: ...uration register see Table 5 53 524h R 0000 0001h CLK_STAT_PWM1 IP clock to PWM 1 in MSCSS status register see Table 5 54 528h R W 0000 0001h CLK_CFG_PWM2 IP clock to PWM 2 in MSCSS configuration regi...

Page 68: ...on register see Table 5 53 904h R 0000 0001h CLK_STAT_TMR0 IP clock to Timer 0 status register see Table 5 54 908h R W 0000 0001h CLK_CFG_TMR1 IP clock to Timer 1 configuration register see Table 5 53...

Page 69: ...CFG_USB_CLK IP clock to USB CLK configuration register see Table 5 53 D04h R 0000 0001h CLK_STAT_USB_CLK IP clock to USB CLK status register see Table 5 54 FF8h 0000 0000h reserved Reserved FFCh A0B6...

Page 70: ...T R 1 Indicator for BASE_SYS_CLK 0 BASE0_STAT R 1 Indicator for BASE_SAFE_CLK Table 52 BASE_STAT register bit description BASE_STAT address 0xFFFF A004 reset value Bit Symbol Access Value Description...

Page 71: ...sses 0xFFFF A104 to 0xFFFF AD04 reset value Bit Symbol Access Value Description 31 to 10 reserved R Reserved do not modify Read as logic 0 9 and 8 SM R Status of state machine controlling the clock en...

Page 72: ...it registers are shown in Table 6 56 The System Control Unit registers have an offset to the base address SCU RegBase which can be found in the memory map see Section 2 2 UM10316 Chapter 6 LPC29xx Sys...

Page 73: ...0h R W 0000 0000h Function select port 5 base address Table 6 57 SFSP5_16 540h R W 0000 0000h Function select port 5 pin 16 USB port 2 USB_D 2 Table 6 59 544h 0000 0000h reserved SFSP5_18 548h R W 000...

Page 74: ...see Table 6 58 SFSPn_6 18h R W 0000 0000h Function select port n pin 6 register see Table 6 58 SFSPn_7 1Ch R W 0000 0000h Function select port n pin 7 register see Table 6 58 SFSPn_8 20h R W 0000 0000...

Page 75: ...6 68h R W 0000 0000h Function select port n pin 26 register see Table 6 58 SFSPn_27 6Ch R W 0000 0000h Function select port n pin 27 register see Table 6 58 SFSPn_28 70h R W 0000 0000h Function select...

Page 76: ...4 When pull up is activated the input is not 5 V tolerant 5 Each pin has up to four functions Setting the FUNC_SEL bits in the SFSP5_16 register also determines the function of port 5 17 If the USB_D...

Page 77: ...on the fly during run time By default it is assigned to function 0 which is the GPIO For each pin of these ports a programmable pull up and pull down resistor R is present Remark Even though the defa...

Page 78: ...master priority registers By default AHB access is scheduled round robin However the AHB access priority of each of the AHB bus masters can be set by writing the priority integer value highest priori...

Page 79: ...ved User manual Rev 00 06 17 December 2008 79 of 571 NXP Semiconductors UM10316 Chapter 6 LPC29xx System Control Unit SCU All masters with the same priority are scheduled on a round robin basis Table...

Page 80: ...the Unique ID of the LPC29xx parts The value will be equal to the JTAG IEEE 1149 1 boundary scan ID Table 7 66 shows the bit assignment of the CHIPID register 2 2 Package information register This con...

Page 81: ...FEAT2 register 2 5 Configuration register 3 This contains a code to identify the configured type of the CFID module It can be used by software to detect different hardware versions of the device Tabl...

Page 82: ...71 NXP Semiconductors UM10316 Chapter 7 LPC29xx Chip Feature ID CFID Table 70 FEAT3 register bit description FEAT3 address 0xE000 010C Bit Symbol Access Value Description 31 JTAGSEC R The setting of t...

Page 83: ...xternal interrupt pins All event inputs are described in Table 8 72 The CAN and LIN receive pin events can be used as extra external interrupt pins when CAN and or LIN functionality is not needed A sc...

Page 84: ...le in the PEND register The wake up CGU and interrupt VIC outputs are active if one of the events is pending 2 1 Event router pin connections The event router module in the LPC29xx is connected to the...

Page 85: ...ART1 RXD IN 20 UART1 receive data input tbd USB_I2C_SCL IN 21 tbd tbd na 22 CAN interrupt internal 1 na 23 VIC FIQ internal 1 na 24 VIC IRQ internal 1 26 to 25 reserved Table 72 Event router pin conne...

Page 86: ...R Reserved do not modify Read as logic 0 26 PEND 26 R 1 An event has occurred on a corresponding pin or logic 1 is written to bit 26 in the INT_SET register 0 No event is pending or logic 1 has been...

Page 87: ...26 MASK 26 R Event enable This bit is set by writing a logic 1 to bit 26 in the MASK_SET register This bit is cleared by writing a logic 1 to bit 26 in the MASK_CLR register 1 0 MASK 0 R Event enable...

Page 88: ...evel sensitive events are expected to be held and removed by the event source Table 8 81 shows the bit assignment of the ATR register 3 9 Raw status register The RSR shows unmasked events including la...

Page 89: ...rights reserved User manual Rev 00 06 17 December 2008 89 of 571 NXP Semiconductors UM10316 Chapter 8 LPC29xx event router Table 82 RSR register bits Bit Symbol Access Value Description 31 to 27 rese...

Page 90: ...ontroller and the various device peripherals are connected to the interrupt request inputs An extensive list of inputs can be found in Table 9 90 The ARM core has two possible interrupt targets IRQ an...

Page 91: ...interrupt request inputs are level sensitive The activation level can be programmed according to the connected peripheral see Table 8 72 for the recommended setting Target IRQ FIQ Two targets are pos...

Page 92: ...on handler should read the INT_VECTOR register to determine the highest priority interrupt source This functionality should be implemented in a dispatcher usually in the assembler This dispatcher perf...

Page 93: ...ING_32_53 Interrupt pending status register see Table 9 88 300h R 0001 0F3F INT_FEATURES Interrupt controller features register see Table 9 89 404h R W INT_REQUEST_1 Interrupt Request 1 control regist...

Page 94: ...see Table 9 91 460h R W INT_REQUEST_24 Interrupt Request 24 control register see Table 9 91 464h R W INT_REQUEST_25 Interrupt Request 25 control register see Table 9 91 468h R W INT_REQUEST_26 Interr...

Page 95: ...4A0h R W INT_REQUEST_40 Interrupt Request 40 control register see Table 9 91 4A4h R W INT_REQUEST_41 Interrupt Request 41 control register see Table 9 91 4A8h R W INT_REQUEST_42 Interrupt Request 42 c...

Page 96: ...32 bit address pointer the table must be aligned to a 512 byte address boundary or 2048 to be future proof If only the index variable is used as offset into the table then this address alignment is n...

Page 97: ...This indicates the lower address boundary of a 512 byte aligned vector table in memory To be compatible with future extension an address boundary of 2048 bytes is recommended 10 and 9 reserved R Reser...

Page 98: ...han it would get by reading the individual interrupt request registers The INT_PENDING_32_63 register is read only Table 9 88 shows the bit assignment of the INT_PENDING_32_63 register 4 5 Interrupt c...

Page 99: ...ch interrupt from timer 0 3 timer 1 Capture or match interrupt from timer 1 4 timer 2 Capture or match interrupt from timer 2 5 timer 3 Capture or match interrupt from timer 3 6 UART 0 General interru...

Page 100: ...rrupt requests Each interrupt line has its own interrupt request register Table 9 91 shows the bit assignment of the INT_REQUEST register 27 Event Router Event wake up tick interrupt from Event Router...

Page 101: ...read as logic 0 29 CLR_SWINT W Clear software interrupt request 1 clears the local software interrupt request state 0 no effect on the local software interrupt request state This bit is always read as...

Page 102: ...has been set 1 The interrupt request may cause an ARM processor interrupt request if further conditions become true 0 The interrupt request is discarded and will not cause an ARM processor interrupt...

Page 103: ...is wake up event is provided by the Event Router The clock domains that can be switched off during idle power mode depend on the selected wake up events For an external interrupt e g EXTINT0 no active...

Page 104: ...ower Ring Oscillator LP_OSC This is required because the clock rate when running at LP_OSC speed is too low for the external debugging environment 5 Functional description of the interrupt and wake up...

Page 105: ...rol 6 Interrupt device architecture In the LPC29xx a general approach is taken to generate interrupt requests towards the CPU A vectored Interrupt Controller VIC receives and collects the interrupt re...

Page 106: ...rovided to set and clear the variable state through a software write action to write only registers These commands are SET_STATUS CLR_STATUS SET_ENABLE and CLR_ENABLE The event signal is logically OR...

Page 107: ...6 1 4 Interrupt enable register This register enables or disables generation of interrupt requests on associated interrupt request output signals INT_ENABLE is a read only register Its content is chan...

Page 108: ...g or disabling the interrupts is dealt with automatically A general rule is to keep atomic actions as small as possible 8 Event service routine ESR Event handling 8 1 ESR functional description This d...

Page 109: ...wer mode selected idle clock domains are switched off The wake up signal towards the CGU enables the clock of these domains A typical application is to configure all clock domains to switch off Since...

Page 110: ...D D R A F T D R A F T D R A F T D R A F T D R A F T D R A F T D R A UM10316_0 NXP B V 2008 All rights reserved User manual Rev 00 06 17 December 2008 110 of 571 NXP Semiconductors UM10316 Chapter 10...

Page 111: ...description tables in this section UM10316 Chapter 11 LPC29xx pin configuration Rev 00 06 17 December 2008 User manual Table 99 Feature overview Part Pin configuration Pin assignment LPC2917 19 01 Fi...

Page 112: ...IO 3 pin 7 SPI2 SCS1 PWM1 MAT1 LIN1 UART RXD P0 30 CAP0 2 MAT0 2 14 1 GPIO 0 pin 30 TIMER0 CAP2 TIMER0 MAT2 P0 31 CAP0 3 MAT0 3 15 1 GPIO 0 pin 31 TIMER0 CAP3 TIMER0 MAT3 P2 24 SCS1 1 PCAP3 1 D22 16 1...

Page 113: ...0 TXD EXTBUS CS4 TMS 36 1 IEEE 1149 1 test mode select pulled up internally TCK 37 1 IEEE 1149 1 test clock P1 21 CAP3 3 CAP1 3 D7 38 1 GPIO 1 pin 21 TIMER3 CAP3 TIMER1 CAP3 MSCSS PAUSE EXTBUS D7 P1 2...

Page 114: ...core VDD CORE 60 1 8 V power supply for digital core P3 13 SDO1 EI5 IDX0 61 1 GPIO 3 pin 13 SPI1 SDO EXTINT5 QEI0 IDX P2 4 MAT1 0 EI0 D12 62 1 GPIO 2 pin 4 TIMER1 MAT0 EXTINT0 EXTBUS D12 P2 5 MAT1 1...

Page 115: ...SPI2 SCS1 PWM3 MAT3 EXTBUS A3 P1 2 SCS2 3 PMAT3 2 A2 86 1 GPIO 1 pin 2 SPI2 SCS3 PWM3 MAT2 EXTBUS A2 P1 1 EI1 PMAT3 1 A1 87 1 GPIO 1 pin 1 EXTINT1 PWM3 MAT1 EXTBUS A1 VSS CORE 88 ground for digital co...

Page 116: ...VREFP 110 3 HIGH reference for ADC VREFN 111 3 LOW reference for ADC P0 8 IN1 0 TX DL0 A20 112 4 GPIO 0 pin 8 ADC1 IN0 LIN0 UART TXD EXTBUS A20 P0 9 IN1 1 RXDL0 A21 113 4 GPIO 0 pin 9 ADC1 IN1 LIN0 U...

Page 117: ...IO 131 3 3 V power supply for I O P0 18 IN2 2 PMAT2 0 A14 132 4 GPIO 0 pin 18 ADC2 IN2 PWM2 MAT0 EXTBUS A14 P0 19 IN2 3 PMAT2 1 A15 133 4 GPIO 0 pin 19 ADC2 IN3 PWM2 MAT1 EXTBUS A15 P3 4 MAT3 2 PMAT2...

Page 118: ...925FBD100 75 26 50 100 76 51 1 25 002aae242 Table 101 LPC2921 23 25 LQFP100 pin assignment Pin name Pin Description Function 0 default Function 1 Function 2 Function 3 TDO 1 1 IEEE 1149 1 test data ou...

Page 119: ...y TCK 26 1 IEEE 1149 1 test clock P1 21 CAP3 3 CAP1 3 27 1 GPIO 1 pin 21 TIMER3 CAP3 TIMER1 CAP3 MSCSS PAUSE P1 20 CAP3 2 SCS0 1 28 1 GPIO 1 pin 20 TIMER3 CAP2 SPI0 SCS1 P1 19 CAP3 1 SCS0 2 29 1 GPIO...

Page 120: ...3 58 1 GPIO 1 pin 3 SPI2 SCS1 PWM3 MAT3 P1 2 SCS2 3 PMAT3 2 59 1 GPIO 1 pin 2 SPI2 SCS3 PWM3 MAT2 P1 1 EI1 PMAT3 1 60 1 GPIO 1 pin 1 EXTINT1 PWM3 MAT1 VSS CORE 61 ground for digital core VDD CORE 62 1...

Page 121: ...13 IN1 5 PMAT1 3 85 4 GPIO 0 pin 13 ADC1 IN5 PWM1 MAT3 P0 14 IN1 6 PMAT1 4 86 4 GPIO 0 pin 14 ADC1 IN6 PWM1 MAT4 P0 15 IN1 7 PMAT1 5 87 4 GPIO 0 pin 15 ADC1 IN7 PWM1 MAT5 P0 16 IN2 0 TXD0 88 4 GPIO 0...

Page 122: ...s in the SCU The functions combined on each port pin are shown in the pin description tables in this section P0 23 IN2 7 PMAT2 5 A19 99 4 GPIO 0 pin 23 ADC2 IN7 PWM2 MAT5 TDI 100 1 IEEE 1149 1 data in...

Page 123: ...MAT2 P0 31 CAP0 3 MAT0 3 15 1 GPIO 0 pin 31 GPIO 0 pin 31 TIMER0 CAP3 TIMER0 MAT3 P2 24 SCS1 1 PCAP3 1 D22 16 1 GPIO 2 pin 24 GPIO 2 pin 24 SPI1 SCS1 PWM3 CAP1 EXTBUS D22 P2 25 SCS1 2 PCAP3 2 D23 17 1...

Page 124: ...D6 39 1 GPIO 1 pin 20 GPIO 1 pin 20 TIMER3 CAP2 SPI0 SCS1 EXTBUS D6 P1 19 CAP3 1 SCS0 2 D5 40 1 GPIO 1 pin 19 GPIO 1 pin 19 TIMER3 CAP1 SPI0 SCS2 EXTBUS D5 P1 18 CAP3 0 SDO0 D4 41 1 GPIO 1 pin 18 GPI...

Page 125: ...2 4 MAT1 0 EI0 D12 62 1 GPIO 2 pin 4 GPIO 2 pin 4 TIMER1 MAT0 EXTINT0 EXTBUS D12 P2 5 MAT1 1 EI1 D13 63 1 GPIO 2 pin 5 GPIO 2 pin 5 TIMER1 MAT1 EXTINT1 EXTBUS D13 P1 9 SDO1 RXDL1 CS1 64 1 GPIO 1 pin 9...

Page 126: ...1 GPIO 1 pin 2 GPIO 1 pin 2 SPI2 SCS3 PWM3 MAT2 EXTBUS A2 P1 1 EI1 PMAT3 1 A1 87 1 GPIO 1 pin 1 GPIO 1 pin 1 EXTINT1 PWM3 MAT1 EXTBUS A1 VSS CORE 88 ground for digital core VDD CORE 89 1 8 V power su...

Page 127: ...rnally VDDA ADC5V0 109 5 V supply voltage for ADC0 and 5 V reference for ADC0 VREFP 110 3 HIGH reference for ADC VREFN 111 3 LOW reference for ADC P0 8 IN1 0 TXDL 0 A20 112 4 GPIO 0 pin 8 GPIO 0 pin 8...

Page 128: ...T1 RXD PWM1 CAP0 EXTBUS BLS3 VDD IO 131 3 3 V power supply for I O P0 18 IN2 2 PMAT2 0 A14 132 4 GPIO 0 pin 18 GPIO 0 pin 18 ADC2 IN2 PWM2 MAT0 EXTBUS A14 P0 19 IN2 3 PMAT2 1 A15 133 4 GPIO 0 pin 19 G...

Page 129: ...2aae253 Table 103 LPC2930 39 LQFP208 pin assignment Pin name Pin Description Function 0 default Function 1 Function 2 Function 3 TDO 1 1 IEEE 1149 1 test data out P2 21 SDI2 PCAP2 1 D19 2 1 GPIO 2 pin...

Page 130: ...P1 TIMER0 MAT1 EXTINT5 VSS IO 27 ground for I O P4 0 A8 28 1 GPIO 4 pin 0 EXTBUS A8 P1 31 CAP0 0 MAT0 0 EI4 29 1 GPIO 1 pin 31 TIMER0 CAP0 TIMER0 MAT0 EXTINT4 P5 0 D8 30 1 GPIO 5 pin 0 EXTBUS D8 P3 8...

Page 131: ...SB_UP_LED1 EXTBUS CS4 TMS 52 1 IEEE 1149 1 test mode select pulled up internally TCK 53 1 IEEE 1149 1 test clock P1 21 CAP3 3 CAP1 3 D7 54 1 GPIO 1 pin 21 TIMER3 CAP3 TIMER1 CAP3 MSCSS PAUSE EXTBUS D7...

Page 132: ...n 14 TIMER2 CAP0 SPI0 SCS3 EXTBUS D0 P4 21 USB_OVRCR2 80 1 GPIO 4 pin 21 USB_OVRCR2 P1 13 SCL1 EI3 WE_N 81 1 GPIO 1 pin 13 EXTINT3 I2C1 SCL EXTBUS WE_N P4 5 A13 82 1 GPIO 4 pin 5 EXTBUS A13 P1 12 SDA1...

Page 133: ...105 1 asynchronous device reset active LOW pulled up internally VSS OSC 106 ground for oscillator XOUT_OSC 107 3 crystal out for oscillator XIN_OSC 108 3 crystal in for oscillator VDD OSC_PLL 109 1 8...

Page 134: ...n 2 EXTBUS D10 P0 3 USB_UP_LED1 PMAT0 1 D27 134 1 GPIO 0 pin 3 USB_UP_LED1 PWM0 MAT1 EXTBUS D27 P4 18 USB_UP_LED2 135 1 GPIO 4 pin 18 USB_UP_LED2 P3 0 IN0 6 PMAT2 0 CS6 136 1 GPIO 3 pin 0 ADC0 IN6 PWM...

Page 135: ...LIN0 TXD UART TXD EXTBUS A20 P0 9 IN1 1 RXDL0 A21 161 4 GPIO 0 pin 9 ADC1 IN1 LIN0 RXD UART TXD EXTBUS A21 P0 10 IN1 2 PMAT1 0 A8 162 4 GPIO 0 pin 10 ADC1 IN2 PWM1 MAT0 EXTBUS A8 P0 11 IN1 3 PMAT1 1...

Page 136: ...GPIO 4 pin 14 BLS3 P5 15 USB_UP_LED1 RTS1 188 1 GPIO 4 pin 14 USB_UP_LED1 UART1 RTS VDD CORE 189 1 8 V power supply for digital core VSS CORE 190 ground for digital core P2 16 TXD1 PCAP0 2 BLS2 191 1...

Page 137: ...TL with Hysteresis Programmable Pull Up Pull Down Repeater 2 USB pad tbd 3 Analog Pad Analog Input Output 4 Analog I O pad tbd P0 22 IN2 6 PMAT2 4 A18 202 4 GPIO 0 pin 22 ADC2 IN6 PWM2 MAT4 EXTBUS A18...

Page 138: ...ntly configurable memory banks simultaneously Each memory bank is capable of supporting SRAM ROM Flash EPROM Burst ROM memory or external I O devices memory mapped Each memory bank may be 8 16 or 32 b...

Page 139: ...s or non address function is accomplished by setting up the SCU Symbol A x refers to the highest order address line of the memory chip used in the external memory interface CS refers to the eight bank...

Page 140: ...Semiconductors UM10316 Chapter 12 LPC29xx external Static Memory Controller SMC 32 bit bank using 16 bit devices Fig 33 External memory interface 32 bit banks with 16 bit devices 32 bit bank using 32...

Page 141: ...ber 2008 141 of 571 NXP Semiconductors UM10316 Chapter 12 LPC29xx external Static Memory Controller SMC 16 bit bank using 8 bit devices Fig 35 External memory interface 16 bit banks with 8 bit devices...

Page 142: ...oth read and write access must be set up These settings should be reconsidered when the ARM processor core clock changes In Figure 12 38 a timing diagram for reading external memory is shown The relat...

Page 143: ...age of the idle turn around time IDCY is demonstrated Extra wait states are added between a read and a write cycle in the same external memory device Address pins on the device are shared with other f...

Page 144: ...0 see Table 12 109 010h R W 4 1h SMBWSTWENR0 Write enable assertion delay control register for memory bank 0 see Table 12 110 014h R W 8 80h SMBCR0 Configuration register for memory bank 0 see Table 1...

Page 145: ...068h R W 8h 00h SMBCR3 Configuration register for memory bank 3 see Table 12 111 06Ch R W 2h 0h SMBSR3 Status register for memory bank 3 see Table 12 112 Bank 4 070h R W 4 Fh SMBIDCYR4 Idle cycle cont...

Page 146: ...106 0ACh R W 5 1Fh SMBWST1R6 Wait state 1 control register for memory bank 6 see Table 12 107 0B0h R W 5 1Fh SMBWST2R6 Wait state 2 control register for memory bank 6 see Table 12 108 0B4h R W 4 0h SM...

Page 147: ...fer wait states in write accesses or in burst read accesses The bank configuration register contains the enable and polarity settings for the external wait Table 106 SMBIDCYRn register bit description...

Page 148: ...le assertion delay control register The bank output enable assertion delay 1 control register configures the delay between the assertion of the chip select and the output enable This delay is used to...

Page 149: ...ENR0 to SMBWSTWENR7 registers 4 6 Bank configuration register The bank configuration register defines bank access for the connected memory device A data transfer can be initiated to the external memor...

Page 150: ...R W Burst mode 1 Sequential access burst reads to a maximum of four consecutive locations is supported to increase the bandwidth by using reduced access time However bursts crossing quad boundaries ar...

Page 151: ...Table 112 SMBSRn register bit description SMBSR0 toSMBSR7 addresses 0x6000 0018 0x6000 0034 0x6000 0050 0x6000 006C 0x6000 0088 0x6000 00A4 0x6000 00C0 0x6000 00DC reset value Bit Symbol Access Value...

Page 152: ...endpoints Each device can have a maximum of 16 logical or 32 physical endpoints There are four types of transfers defined for the endpoints Control transfers are used to configure the device Interrupt...

Page 153: ...d Isochronous endpoints 4 Fixed endpoint configuration Table 13 114 shows the supported endpoint configurations Endpoints are realized and configured at run time using the Endpoint realization registe...

Page 154: ...023 Yes 9 19 Isochronous In 1 to 1023 Yes 10 20 Interrupt Out 1 to 64 No 10 21 Interrupt In 1 to 64 No 11 22 Bulk Out 8 16 32 64 Yes 11 23 Bulk In 8 16 32 64 Yes 12 24 Isochronous Out 1 to 1023 Yes 12...

Page 155: ...cket size of the endpoint and whether the endpoint supports double buffering 5 4 EP_RAM access control The EP_RAM Access Control logic handles transfer of data from to the EP_RAM and the three sources...

Page 156: ...er For an OUT transaction the USB ATX receives the bi directional D and D signals of the USB bus The Serial Interface Engine SIE receives the serial data from the ATX and converts it into a parallel d...

Page 157: ...se When the USB Device Controller goes into the suspend state bus is idle for 3 ms the usbclk input to the device controller is automatically disabled helping to conserve power However if software wis...

Page 158: ...Power down mode 8 4 Remote wake up The USB device controller supports software initiated remote wake up Remote wake up involves resume signaling on the USB bus initiated from the device This is done b...

Page 159: ...E010 C210 USBCmdData USB Command Data RO 0x0000 0000 0xE010 C214 DMA registers USBDMARSt USB DMA Request Status RO 0x0000 0000 0xE010 C250 USBDMARClr USB DMA Request Clear WO 2 0x0000 0000 0xE010 C254...

Page 160: ...form the USB_NEED_CLK signal When enabling a clock via USBClkCtrl software should poll the corresponding bit in USBClkSt If it is set then software can go ahead with the register access Software does...

Page 161: ...F8 bit description Bit Symbol Description Reset value Table 120 USB Interrupt Status register USBIntSt address tbd bit description Bit Symbol Description Reset value 0 USB_INT_REQ_LP Low priority inte...

Page 162: ...t is set the corresponding endpoint interrupt will be routed to this bit 0 2 EP_SLOW Slow endpoints interrupt If an Endpoint Interrupt Priority Register USBEpIntPri bit is not set the corresponding en...

Page 163: ...EP_SLOW EP_FAST FRAME Table 124 USB Device Interrupt Enable register USBDevIntEn address 0xE010 C204 bit description Bit Symbol Value Description Reset value 31 0 See USBDevIntEn bit allocation table...

Page 164: ...endpoints generate an interrupt when they receive a packet without an error All non isochronous IN endpoints generate an interrupt when a packet is successfully transmitted or when a NAK handshake is...

Page 165: ...scription Reset value 0 EP0RX Endpoint 0 Data Received Interrupt bit 0 1 EP0TX Endpoint 0 Data Transmitted Interrupt bit or sent a NAK 0 2 EP1RX Endpoint 1 Data Received Interrupt bit 0 3 EP1TX Endpoi...

Page 166: ...hould wait for CDFULL to be set to ensure the corresponding interrupt has been cleared before proceeding 25 EP12TX Endpoint 12 Isochronous endpoint NA 26 EP13RX Endpoint 13 Data Received Interrupt bit...

Page 167: ...Each endpoint has its own bit in this register USBEpIntSet is a write only register Table 134 USB Endpoint Interrupt Clear register USBEpIntClr address 0xE010 C238 bit allocation Reset value 0x0000 00...

Page 168: ...ce required for an endpoint depends on its MaxPacketSize and whether it is double buffered 32 words of EP_RAM are used by the device for storing the endpoint buffer pointers The EP_RAM is word aligned...

Page 169: ...onding endpoint to be realized Writing zeros causes it to be unrealized This register returns to its reset state when a bus reset occurs USBReEp is a read write register EPRAMspace MaxPacketSize 3 4 1...

Page 170: ...egister USBEpMaxPSize MPS check whether the EP_RLZED bit in the Device Interrupt Status register is set while USBDevIntSt EP_RLZED wait until endpoint realization is complete Clear the EP_RLZED bit Cl...

Page 171: ...ve mode operation See Section 13 13 Slave mode operation 9 5 1 USB Receive Data register USBRxData 0xE010 C218 For an OUT transaction the CPU reads the endpoint buffer data from this register Before r...

Page 172: ...from the CPU to the selected endpoint buffer Before writing data to USBTxData software should first write the packet length MaxPacketSize to this register After each write to USBTxData hardware decrem...

Page 173: ...ption Bit Symbol Value Description Reset value 9 0 PKT_LNGTH The remaining number of bytes to be written to the selected endpoint buffer This field is decremented by 4 by hardware after each write to...

Page 174: ...hardware when an endpoint interrupt occurs see the description of USBEpIntSt and the corresponding bit in USBEpIntEn is 0 A bit associated with an isochronous endpoint is set when the corresponding b...

Page 175: ...in this register sets the corresponding bit in the USBDMARSt register Writing zero has no effect Table 151 USB DMA Request Status register USBDMARSt address 0xE010 C250 bit allocation Reset value 0x00...

Page 176: ...mmunication Area Head register maintains the address where the UDCA is located in the USB RAM Refer to Section 13 14 2 USB device communication area and Section 13 14 4 The DMA descriptor for more det...

Page 177: ...ndpoint when its corresponding bit is cleared the transfer is completed before the DMA is disabled When an error condition is detected during a DMA transfer the corresponding bit is cleared by hardwar...

Page 178: ...endpoint and the EP0_DMA_DISABLE bit value must be 0 0 1 EP1_DMA_DISABLE 0 Control endpoint IN DMA cannot be enabled for this endpoint and the EP1_DMA_DISABLE bit value must be 0 0 31 2 EPxx_DMA_DISAB...

Page 179: ...ts the corresponding bit in the USBEoTIntSt register Writing zero has no effect USBEoTIntSet is a write only register 1 NDDR New DD Request Interrupt enable bit 0 0 The New DD Request Interrupt is dis...

Page 180: ...USBNDDRIntSet is a write only register Table 163 USB End of Transfer Interrupt Set register USBEoTIntSet address 0xE010 C2A8 bit description Bit Symbol Value Description Reset value 31 0 EPxx Set endp...

Page 181: ...Writing zero has no effect USBSysErrIntSet is a write only register 10 Interrupt handling This section describes how an interrupt event on any of the endpoints is routed to the Nested Vectored Interr...

Page 182: ...nabled in USBDevIntEn are routed to the USB_INT_REQ_LP bit in the USBIntSt register to request low priority interrupt handling However the USBDevIntPri register can route either the FRAME or the EP_FA...

Page 183: ...nductors UM10316 Chapter 13 LPC29xx USB device For simplicity USBDevIntEn and USBDMAIntEn are not shown Fig 43 Interrupt event handling USB_INT_REQ_HP USB_INT_REQ_LP USB_INT_REQ_DMA EN_USB_INTS to NVI...

Page 184: ...PHASE field set to the value 0x02 Read and the CMD_CODE field set with command code the read corresponds to On completion of the read the CDFULL bit of USBDevInSt will be set indicating the data is av...

Page 185: ...mand code table Command name Recipient Code Hex Data phase Device commands Set Address Device D0 Write 1 byte Configure Device Device D8 Write 1 byte Set Mode Device F3 Write 1 byte Read Current Frame...

Page 186: ...s functional the 48 MHz clock can be stopped when the device enters suspend state 1 USB_NEED_CLK is fixed to 1 the 48 MHz clock cannot be stopped when the device enters suspend state 1 INAK_CI Interru...

Page 187: ...Device Status Command 0xFE Data write 1 byte The Set Device Status command sets bits in the Device Status Register Table 174 Set Device Status Register bit description Bit Symbol Value Description Res...

Page 188: ...e 3 SUS_CH Suspend SUS bit change indicator The SUS bit can toggle because The device goes into the suspended state The device is disconnected The device receives resume signalling on its upstream por...

Page 189: ...Error 0010 Unknown PID 0011 Unexpected Packet any packet sequence violation from the specification 0100 Error in Token CRC 0101 Error in Data CRC 0110 Time Out Error 0111 Babble 1000 Error in End of...

Page 190: ...he B_1_FULL and B_2_FULL bits For single buffered endpoints this bit simply reflects the status of B_1_FULL 0 0 For an IN endpoint at least one write endpoint buffer is empty 1 For an OUT endpoint at...

Page 191: ...ical endpoint number in hex Not all bits can be set for all types of endpoints 6 B_2_FULL The buffer 2 status 0 0 Buffer 2 is empty 1 Buffer 2 is full 7 Reserved user software should not write ones to...

Page 192: ...Clear Interrupt command read the new SETUP data and again check the status of the PO bit See Section 13 13 Slave mode operation for a description of when this command is used 11 14 Validate Buffer Com...

Page 193: ...ler clocks by setting DEV_CLK_EN and AHB_CLK_EN bits in the USBClkCtrl register Poll the respective clock bits in the USBClkSt register until they are set 4 Enable the USB pin functions by writing to...

Page 194: ...he USBEpIntEn register and are observable in the USBEpIntSt register All non isochronous OUT endpoints generate an endpoint interrupt when they receive a packet without an error All non isochronous IN...

Page 195: ...ogical endpoint Interleaved read and write operation is possible 14 DMA operation In DMA mode the DMA transfers data between RAM and the endpoint buffer The following sections discuss DMA mode operati...

Page 196: ...by setting the corresponding bit in the USBEpIntEn register to 0 Section 13 9 3 2 and an endpoint interrupt occurs see Section 13 9 7 1 USB DMA Request Status register USBDMARSt 0xE010 C250 A DMA tran...

Page 197: ...DDs for isochronous endpoints are five words long The parameters associated with a DMA transfer are The start address of the DMA buffer The length of the DMA buffer The start address of the next DMA...

Page 198: ...es the new descriptor when it is finished with the current one 14 4 4 Isochronous_endpoint When set this bit indicates that the descriptor belongs to an isochronous endpoint Hence 5 words have to be r...

Page 199: ...ield The following codes are defined NotServiced No packet has been transferred yet BeingServiced At least one packet is transferred NormalCompletion The DD is retired because the end of the buffer is...

Page 200: ...This is applicable only for OUT endpoints Offset 0 indicates that the message length starts from the first byte of the first packet 14 4 15 Isochronous_packetsize_memory_address The memory buffer add...

Page 201: ...UT endpoints the current packet is read from the EP_RAM by the DMA Engine and transferred to the USB RAM memory locations starting from DMA_buffer_start_addr For IN endpoints the data is fetched from...

Page 202: ...by setting both the Max_packet_size and DMA_buffer_length fields in the DD to 0 On processing a No_Packet DD the DMA engine clears the DMA request bit in USBDMARSt corresponding to the endpoint withou...

Page 203: ...th field of the isochronous packet size word is used For each frame an isochronous data packet of size specified by this field is transferred from the USB device to the host and Isochronous_packet_siz...

Page 204: ...this concatenated transfer back into the original delta transfers and transfer them to separate DMA buffers This is achieved by setting the DMA mode to Auto Transfer Length Extraction ATLE mode in th...

Page 205: ...B transfer specified by Message_length_position from the incoming data packets and writes it in the DMA_buffer_length field of the DD To ensure that both bytes of the DMA_buffer_length are extracted i...

Page 206: ...are sent as a short packet on USB which marks the end of the USB transfer for the host If the last buffer length completes on a MaxPacketSize packet boundary the device software must program the next...

Page 207: ...length is 0 an empty packet will be sent to indicate the end of the USB transfer 15 Double buffered endpoint operation The Bulk and Isochronous endpoints of the USB Device Controller are double buffe...

Page 208: ...ccur The active buffer is now B_2 The next data packet sent by the host will be placed in B_2 The following example illustrates how double buffering works for a Bulk IN endpoint in Slave mode Assume t...

Page 209: ...anually starting a packet transfer using the USBDMARSet register 15 2 Isochronous endpoints For isochronous endpoints the active data buffer is switched by hardware when the FRAME interrupt occurs The...

Page 210: ...ntroller The host controller enables data exchange with various USB devices attached to the bus It consists of register interface serial interface engine and DMA controller The register interface comp...

Page 211: ...HB slave AHB bus HOST CONTROLLER ATX CONTROL LOGIC PORT MUX port 1 port 2 U2 port U1 port USB HOST BLOCK Table 182 USB OTG port pins Pin name Direction Description Pin category USB_VBUS I VBUS status...

Page 212: ...of the version of the HCI specification that is implemented by the Host Controller 0x10 HcControl 0xE010 C004 R W Defines the operating modes of the HC 0x0 HcCommandStatus 0xE010 C008 R W This regist...

Page 213: ...t counter and provides the timing reference among events happening in the HC and the HCD 0x0 HcPeriodicStart 0xE010 C040 R W Contains a programmable 14 bit value which determines the earliest time HC...

Page 214: ...rmation on USB OTG can be found on the USB Implementers Forum web site 3 Features Fully compliant with On The Go supplement to the USB 2 0 Specification Revision 1 0a Hardware support for Host Negotia...

Page 215: ...E CONTROLLER HOST CONTROLLER EP_RAM OTG CONTROLLER ATX CONTROL LOGIC PORT MUX USB port OTG TRANSCEIVER USB OTG BLOCK Table 185 USB OTG port pins Pin name Direction Description Interfacing Port 1 USB_V...

Page 216: ...Remark To select the USB functions see the SPSP registers in Table 6 58 Table 6 59 and Table 6 60 For input only pins e g USB_OVRCR select PAD_TYPE in the corresponding SFSP register to digital input...

Page 217: ...rface 5 1 Suggested USB interface solutions Fig 49 LPC29xx USB OTG port configuration USB port 1 OTG dual role device USB port 2 host USB_UP_LED1 USB_D 1 USB_D 1 USB_PWRD2 USB_SDA1 USB_SCL1 USB_RST1 1...

Page 218: ...218 of 571 NXP Semiconductors UM10316 Chapter 15 LPC29xx USB OTG interface Fig 50 LPC29xx USB OTG port configuration USB port 1 host USB port 2 host USB_UP_LED1 USB_D 1 USB_D 1 USB_PWRD1 USB_PWRD2 15...

Page 219: ...s wide and aligned to word address boundaries Fig 51 LPC29xx USB OTG port configuration USB port 2 device USB port 1 host USB_UP_LED1 USB_D 1 USB_D 1 USB_PWRD1 15 k 15 k LPC293X USB A connector USB B...

Page 220: ...LKLO 0xE010 C310 WO I2C Clock Low Clock control registers OTGClkCtrl 0xE010 CFF4 R W OTG clock controller OTGClkSt 0xE010 CFF8 RO OTG clock status Table 186 USB OTG and I2C register address definition...

Page 221: ...atus and Control Register OTGStCtrl 0xE010 C110 The OTGStCtrl register allows enabling hardware tracking during the HNP hand over sequence controlling the OTG timer monitoring the timer count and cont...

Page 222: ...to this bit resets TMR_CNT to 0 This provides a single bit control for the software to restart the timer when the timer is enabled 0 7 Reserved user software should not write ones to reserved bits The...

Page 223: ...go ahead with the register access Software does not have to repeat this exercise for every access provided that the OTGClkCtrl bits are not disturbed Table 191 OTG_clock_control register OTG_clock_co...

Page 224: ...ceive in the RX FIFO When the STOP bit is set or the START bit is set to cause a RESTART condition on a byte written to the TX FIFO master receiver then the byte read from the slave is not acknowledge...

Page 225: ...of data is sent the transmitter expects an acknowledge from the receiver This bit is set if the acknowledge is not received It is cleared when a byte is written to the master TX FIFO 0 0 Last transmi...

Page 226: ...is empty 10 TFF Transmit FIFO Full TFF is set when the TX FIFO is full and is cleared when the TX FIFO is not full 0 0 TX FIFO is not full 1 TX FIFO is full 11 TFE Transmit FIFO Empty TFE is set when...

Page 227: ...terrupt Enable This enables the DAI interrupt to indicate that data is available in the receive FIFO i e not empty 0 0 Disable the DAI 1 Enable the DAI 7 TFFIE Transmit FIFO Not Full Interrupt Enable...

Page 228: ...ntroller see the USB device chapter For interrupts created by the host controllers see the OHCI specification The EN_USB_INTS bit in the USBIntSt register enables the routing of any of the USB related...

Page 229: ...Host A device and the default Peripheral B device can switch Host and Peripheral roles using HNP The context of the OTG controller operation is shown in Figure 15 53 Each controller Host Device or OTG...

Page 230: ...lement defines the behavior of a dual role B device during HNP using a state machine diagram The OTG software stack is responsible for implementing all of the states in the Dual Role B Device State Di...

Page 231: ...B Device states is also shown B device states are in bold font with a circle around them Fig 54 Hardware support for B device switching from peripheral state to host state idle set HNP_SUCCESS set POR...

Page 232: ...ld be polled but this is not necessary if the corresponding interrupt is enabled Following are code examples that show how the actions in Figure 15 55 are accomplished The examples assume that ISP1301...

Page 233: ...TDI to be set while OTG_I2C_STS TDI Clear TDI OTG_I2C_STS TDI 7 2 A device host to peripheral HNP switching In this case the role of the OTG controller is host A device and the A device switches role...

Page 234: ...hardware actions setting TMR HNP_SUCCESS and HNP_FAILURE The relationship of the software actions to the Dual Role A Device states is also shown A device states are shown in bold font with a circle ar...

Page 235: ...d be polled but this is not necessary if the corresponding interrupt is enabled Following are code examples that show how the actions in Figure 15 57 are accomplished The examples assume that ISP1301...

Page 236: ...Clear BDIS_ACON_EN in external OTG transceiver Set BDIS_ACON_EN in ISP1301 OTG_I2C_TX 0x15A Send ISP1301 address R W 0 OTG_I2C_TX 0x005 Send Mode Control 1 Clear register address OTG_I2C_TX 0x210 Clea...

Page 237: ...ake The host stack code where this is done will be somewhat more involved HC_RH_PORT_STAT1 PSS 8 Clocking and power management The OTG controller clocking is shown in Figure 15 58 Note that the host c...

Page 238: ...activity is detected on the USB bus The dev_need_clk signal is de asserted if a disconnect is detected CON bit is cleared in the SIE Get Device Status register This signal allows DEV_CLK_EN to be clea...

Page 239: ...in Figure 15 58 A clock switch controls each clock with the exception of ahb_slave_clk When the enable of the clock switch is asserted its clock output is turned on and its CLK_ON output is asserted...

Page 240: ...y is detected on the USB bus The dev_need_clk signal is de asserted if a disconnect is detected CON bit is cleared in the SIE Get Device Status register Section 13 11 7 This signal allows DEV_CLK_EN t...

Page 241: ...ts clock when it goes into the UsbSuspend state The host_dma_need_clk signal is asserted on any Host controller DMA access to memory Once asserted it remains active for 2 ms 2 frames to help assure th...

Page 242: ...n be found in Ref 32 1 A number of points should be noted in regard to SCU mapping of GPIO pins If an input port is not mapped through the SCU to an external I O pin it is assigned a logical 0 If an o...

Page 243: ...direction as output to drive a LOW voltage level logic 0 Configuring the pin direction as input to provide an open drain In this case the other devices and external resistor determine the voltage leve...

Page 244: ...ividually control each I O pin output driver enable If the port is configured as input see Table 6 58 to configure the appropriate pad type Table 16 203 shows the bit assignment of the DR register Bit...

Page 245: ...of 571 NXP Semiconductors UM10316 Chapter 16 LPC29xx General Purpose Input Output GPIO Table 203 DR register bit description DR0 to 5 addresses 0xE004 A008 GPIO0 0xE004 B008 GPIO1 0xE004 C008 GPIO2 0x...

Page 246: ...Timer functional description The timers can be used to measure the time between events An interrupt can be generated When a predetermined period has elapsed match functionality see section Section 17...

Page 247: ...ented Both events occur at the next system clock cycle so effectively the timer counter is incremented at every prescale value 1 cycle of the system clock When the timer counter equals a match value M...

Page 248: ...match the external match pins go to the setting selected via the EMR register 4 1 Timer capture functionality The timer block contains four capture circuits The capture functionality allows measuring...

Page 249: ...7 205 004h R W 0000 0000h TC Timer counter value see Table 20 253 008h R W 0000 0000h PR Prescale register see Table 20 254 00Ch R W 000h MCR Match control register see Table 17 208 010h R W 000h EMR...

Page 250: ...od of CLK_TMRx this means that the contents of the register can change very rapidly FE8h W INT_CLR_STATUS Interrupt clear status register see Table 10 97 FECh W INT_SET_STATUS Interrupt set status reg...

Page 251: ...er and prescale counter This maintains their value at the time of the match to restart the timer counter at logic 0 and allows the counters to continue counting and or generate an interrupt when their...

Page 252: ...if MR2 matches TC 0 3 STOP_1 R W 1 Stop on match MR1 and TC When logic 1 the timer and prescale counter stop counting if MR1 matches TC 0 2 RESET_1 R W 1 Reset on match MR1 and TC When logic 1 the ti...

Page 253: ...sequence is detected the timer counter value is loaded into the capture register If it has been enabled through the interrupt enable control register an interrupt is then generated Setting both the r...

Page 254: ...auses CR2 to be loaded with the contents of TC 0 4 RISE_2 R W 1 Capture on capture input 2 rising When logic 1 a sequence of logic 0 followed by logic 1 from capture input 2 causes CR2 to be loaded wi...

Page 255: ...The first column gives the bit number i in the interrupt registers For a general explanation of the interrupt concept and a description of the registers see Section 10 5 Table 212 CR register bits re...

Page 256: ...ffers each 16 bits wide by 32 locations deep Programmable choice of interface operation Motorola SPI or Texas Instruments synchronous serial interfaces Programmable data frame size from four to16 bits...

Page 257: ...ple in Figure 18 64 the SPI module supports addressing of four slaves all of which are sent data in sequential slave mode Three elements are transferred to slave 1 two to slave 2 three to slave 3 and...

Page 258: ...his slave and the other settings are needed to create the delay of the suspended transfer on the serial interface Suspending a slave does not change anything in the duration of a sequential slave tran...

Page 259: ...000 0020h SLV0_SETTINGS1 Slave settings register 1 for slave 0 see Table 18 223 028h R W 0000 0000h SLV0_SETTINGS2 Slave settings register 2 for slave 0 see Table 18 224 02Ch R W 0000 0020h SLV1_SETTI...

Page 260: ...ed when the new value is in use In sequential slave mode the newly programmed value will be used when the pending sequential slave transfer finishes In normal transmission mode the newly programmed va...

Page 261: ...Transmit mode 1 Sequential slave mode 0 Normal mode 2 LOOPBACK_MODE R W Loopback mode bit Note when the RX FIFO width is smaller than the TX FIFO width the most significant bits of the transmitted dat...

Page 262: ...register bit description SLV_ENABLE0 1 2 addresses 0xE004 7004 SPI0 0xE004 8004 SPI1 0xE004 9004 SPI2 reset value Bit Symbol Access Value Description 31 to 8 reserved R Reserved do not modify Read as...

Page 263: ...able 218 FIFO_DATA register bit description FIFO_DATA0 1 2 addresses 0xE004 700C SPI0 0xE004 800C SPI1 0xE004 900C SPI2 reset value Bit Symbol Access Value Description 31 to 16 reserved R Reserved do...

Page 264: ...the FIFO_DATA register will return the data from the FIFO but will not update the FIFO s read pointer Speculative reads of the FIFO_DATA register will thus not cause data loss from the receive FIFO Af...

Page 265: ...RX_DMA ENABLE R W Rx DMA enable bit 1 DMA enabled 0 DMA disabled Table 221 DMA_SETTINGS register bit description DMA_SETTINGS0 1 2 addresses 0xE004 7018 SPI0 0xE004 8018 SPI1 0xE004 9018 SPI2 continue...

Page 266: ...mit FIFO empty 0 Transmit FIFO not empty Table 222 SPI status register bit description STATUS0 1 2 addresses 0xE004 701C SPI0 0xE004 801C SPI1 0xE004 901C SPI2 continued reset value Bit Symbol Access...

Page 267: ...ify Read as logic 0 16 to 9 PRE_POST_CS_DLY R W Programmable delay that occurs twice in a transfer This delay is present i between assertion of the chip select and transfer sampling of the first data...

Page 268: ...to service the FIFOs Table 18 225 shows the bit assignment of the INT_THRESHOLD register 5 SPH R W Serial clock phase only used if Motorola SPI mode is selected Determines which edges of the serial cl...

Page 269: ...description INT_THRESHOLD addresses 0xE004 7FD4 SPI0 0xE004 8FD4 SPI1 0xE004 9FD4 SPI2 reset value Bit Symbol Access Value Description 31 to 16 reserved R Reserved do not modify Read as logic 0 15 to...

Page 270: ...Asynchronous Receiver Transmitter UART Rev 00 06 17 December 2008 User manual Table 227 UART0 1 Pin description Pin Type Description UART0 RXD UART1 RXD Input Serial Input Serial receive data UART0 TX...

Page 271: ...upt if enabled IER 3 1 UART0 1 DTR Output Data Terminal Ready Active low signal indicates that the UART1 is ready to establish connection with external modem The complement value of this signal is sto...

Page 272: ...rite Data WO NA U0THR 0xE004 5000 U1THR 0xE004 6000 DLL DLAB 1 Divisor Latch LSB 8 bit Data R W 0x01 U0DLL 0xE004 5000 U1DLL 0xE004 6000 DLM DLAB 1 Divisor Latch MSB 8 bit Data R W 0x00 U0DLM 0xE004 5...

Page 273: ...the data stored in used bits only It does not include reserved bits content ACR Auto baud Control Register Reserved 31 10 ABTO IntClr ABEO IntClr R W 0x00 U0ACR 0xE004 5020 U1ACR 0xE004 6020 Reserved...

Page 274: ...AB in UnLCR must be zero in order to access the UnTHR The UnTHR is always Write Only 4 3 UARTn Divisor Latch LSB Register The UARTn Divisor Latch is part of the UARTn Baud Rate Generator and holds the...

Page 275: ...ble 233 UARTn Interrupt Enable Register U0IER address 0xE004 5004 U1IER 0xE004 6004 when DLAB 0 bit description Bit Symbol Value Description Reset Value 0 RBR Interrupt Enable enables the Receive Data...

Page 276: ...4 1 The interrupt is cleared upon an UnLSR read The UARTn RDA interrupt UnIIR 3 1 010 shares the second level priority with the CTI interrupt UnIIR 3 1 110 The RDA is activated when the UARTn Rx FIFO...

Page 277: ...01 is a third level interrupt and is activated when the UARTn THR FIFO is empty provided certain initialization conditions have been met These initialization conditions are intended to give the UARTn...

Page 278: ...this bit will automatically clear the UARTn FIFOs 1 RX FIFO Reset 0 No impact on either of UARTn FIFOs 0 1 Writing a logic 1 to UnFCR 1 will clear all bytes in UARTn Rx FIFO and reset the pointer logi...

Page 279: ...sable parity generation and checking 0 1 Enable parity generation and checking 5 4 Parity Select 00 Odd parity Number of 1s in the transmitted character and the attached parity bit will be odd 0 01 Ev...

Page 280: ...o the sending UART to continue transmitting data If Auto RTS mode is disabled the RTSen bit controls the RTS output of the UART If Auto RTS mode is enabled hardware controls the RTS output and the act...

Page 281: ...byte CTS must be released before the middle of the last stop bit that is currently being sent In Auto CTS mode a change of the CTS signal does not trigger a modem status interrupt unless the CTS Inter...

Page 282: ...ts0 7 start bits0 7 stop start bits0 7 stop UART1 TX CTS1 pin stop Table 240 UARTn Line Status Register U0LSR address 0xE004 5014 U1LSR 0xE004 6014 Read Only bit description Bit Symbol Value Descripti...

Page 283: ...ror status is active 4 Break Interrupt BI 0 When RXDn is held in the spacing state all 0 s for one full character transmission start data parity stop a break interrupt occurs Once the break condition...

Page 284: ...upon state change of input CTS Cleared on an MSR read 0 0 No change detected on modem input CTS 1 State change detected on modem input CTS 1 Delta DSR Set upon state change of input DSR Cleared on an...

Page 285: ...f the UARTn Rx pin the length of the start bit The UnACR AutoRestart bit can be used to automatically restart baud rate measurement if a time out occurs the rate measurement counter overflows If this...

Page 286: ...ed character format and sets the UnACR Start bit The initial values in the divisor latches UnDLM and UnDLM don t care Because of the A or a ASCII coding A 0x41 a 0x61 the UARTn Rx pin sensed start bit...

Page 287: ...written at the user s discretion This pre scaler takes the APB clock and generates an output clock according to the specified fractional requirements Important If the fractional divider is active DIV...

Page 288: ...lost or corrupted If the U0 1FDR register value does not comply to these two requests then the fractional divider output is undefined If DIVADDVAL is zero then the fractional divider is disabled and...

Page 289: ...71 NXP Semiconductors UM10316 Chapter 19 LPC29xx Universal Asynchronous Receiver Transmitter Fig 68 Algorithm for setting UART dividers PCLK BR Calculating UART baudrate BR DL est PCLK 16 x BR DLest i...

Page 290: ...and MULVAL 8 Based on these findings the suggested UART setup would be DLM 0 DLL 4 DIVADDVAL 5 and MULVAL 8 According to Equation 19 2 UART s is 115384 This rate has a relative error of 0 16 from the...

Page 291: ...ftware should not write ones to reserved bits The value read from a reserved bit is not defined NA 7 TXEN When this bit is 1 as it is after a Reset data written to the THR is output on the TXD pin as...

Page 292: ...lowing data While the receiver is ENABLED RS485CTRL bit 1 0 all received bytes will be accepted and stored in the RXFIFO regardless of whether they are data or address When an address character is rec...

Page 293: ...S485CTRL bit 4 takes precedence over all other mechanisms controlling RTS or DTR with the exception of loopback mode RS485 EIA 485 driver delay time The driver delay time is the delay between the last...

Page 294: ...n Baud Rate Generator block UnBRG generates the timing enables used by the UARTn TX block The UnBRG clock input source is the APB clock BASE_UART_CLK The main clock is divided down per the divisor spe...

Page 295: ...V 2008 All rights reserved User manual Rev 00 06 17 December 2008 295 of 571 NXP Semiconductors UM10316 Chapter 19 LPC29xx Universal Asynchronous Receiver Transmitter Fig 69 UART0 1 block diagram APB...

Page 296: ...t register Another way to prevent resets during debug mode is via the pause feature of the Watchdog timer The Watchdog is stalled when the ARM9 is in debug mode and the PAUSE_ENABLE bit in the Watchdo...

Page 297: ...The timer registers have an offset to the base address WDT RegBase This can be found in the memory map see Section 2 2 4 Write 0x251D8951 key exor counter_enable to the Watchdog Timer Control register...

Page 298: ...ng as the COUNTER_RESET bit is active FD4h R 0000 00C8h reserved Reserved FD8h W 0000 0101h INT_CLR_ENABLE Interrupt clear enable register see Table 10 93 FDCh W INT_SET_ENABLE Interrupt set enable re...

Page 299: ...ne then increments the TC_value Updates to the prescale register are only possible when the timer and prescale counters are disabled see bit COUNTER_ENABLE in the TCR register It is advisable to reset...

Page 300: ...grammed value To be able to write to this register it must be unlocked first This is done by first writing to this register the key word as stored in the Watchdog_Key register Updating the Watchdog_Ti...

Page 301: ...gisters For a general explanation of the interrupt concept and a description of the registers see Section 10 5 Table 257 WD_DEBUG register bit description WD_DEBUG address 0xE004 0040 reset value Bit...

Page 302: ...ance filter before they reach the CAN controller The acceptance filter fetches information on which message should be filtered from the ID look up table The status of all CAN controllers is summarized...

Page 303: ...hronization jump width To compensate for phase shifts between the clock oscillators of different bus controllers any bus controller must resynchronize on any relevant signal edge of the current transm...

Page 304: ...ows definition of a priority for each transmit buffer see Section 21 5 2 for more details The identifier register contains the message ID Depending on the chosen frame format an 11 bit identifier for...

Page 305: ...ave not been released before a new message arrives and passes through the acceptance filter The data overrun situation is signaled via the DOS bit in the global status register CCGS and by the data ov...

Page 306: ...rrupt are generated if enabled 7 1 Global self test A global self test can for example verify the used configuration in a given CAN system As shown in Figure 21 72 at least one other CAN node which ac...

Page 307: ...type see Table 21 259 Five start address registers exist to indicate the boundaries of the different sections within the ID look up table memory These registers store the offset for the base address C...

Page 308: ...k up table memory 001aaa175 29 BIT index h i j k l 1 LOWER BOUND 29 BIT index h i j k UPPER BOUND 11 BIT index h i LOWER BOUND 11 BIT index h i UPPER BOUND 11 BIT index h i j 1 LOWER BOUND 11 BIT inde...

Page 309: ...al state machine and by the CPU there is a method for ensuring that no CPU reads from a FullCAN message object occurring while the internal state machine is writing to that object The acceptance filte...

Page 310: ...n In the case of SEM 1 0 unequal to 00 the message object has been changed during reading so the contents of the message object should be read out once again If on the other hand SEM 1 0 00 as expecte...

Page 311: ...enabled only the message disable bits in the acceptance filter look up table memory can be changed by software Note that in this section the lower bound and upper bound message disable bit must alway...

Page 312: ...gure 21 75 Refer to it for resolving register register slice and bit names 8 7 CAN acceptance filter mode register The ACCBP and ACCOFF bits of the acceptance filter mode register CAMODE are used for...

Page 313: ...ier sections The end of table address also assigns the start address of the section where FullCAN message objects if enabled are stored See also the example in Section 21 13 A write access to all sect...

Page 314: ...s where equal message identifiers of the same frame format are defined in more than one section the first match ends the screening process for this identifier For example if the same source CAN channe...

Page 315: ...er status register are bundled together For example the Tx status of all CAN controllers can be read at once with one 32 bit word access The status registers are read only and allow byte half word and...

Page 316: ...1 280 44h R W 0000 0000h CCTXB2ID CAN controller transmit buffer 2 identifier register see Table 21 281 48h R W 0000 0000h CCTXB2DA CAN controller transmit buffer 2 data A register see Table 21 282 4C...

Page 317: ...it assignment of the CCMODE register 0Ch R W 000h CAEFESA CAN acceptance filter extended frame explicit start address register see Table 21 287 10h R W 000h CAEFGSA CAN acceptance filter extended fram...

Page 318: ...reset mode it is not possible to access any other register within the same instruction Table 267 CCMODE register bit description CCMODE address 0xE008 0000 CAN0 and 0xE008 1000 CAN1 reset value both...

Page 319: ...buffer 3 is selected for transmission 6 STB2 W Select transmit buffer 2 1 Transmit buffer 2 is selected for transmission 5 STB1 W Select transmit buffer 1 1 Transmit buffer 1 is selected for transmiss...

Page 320: ...the CPU requires suspension of the previously requested transmission e g to transmit a more urgent message first A transmission already in progress is not stopped To see if the original message has be...

Page 321: ...TCS 4 R Transmission complete status 1 All requested message transmissions have completed successfully 0 At least one of the previously requested transmissions has not yet completed 2 TBS R Transmit b...

Page 322: ...the CAN bus is idle If both bits are set the controller is waiting to become idle again After hardware reset 11 consecutive recessive bits have to be detected until idle status is reached After bus o...

Page 323: ...h 11 arbitration lost in SRTR bit RTR bit for standard frame messages 0Ch 12 arbitration lost in IDE bit 13 arbitration lost in 12th bit of identifier extended frame only 1Eh 30 arbitration lost in la...

Page 324: ...he arbitration lost interrupt enable is set 0 5 EPI R Error passive interrupt 1 The CAN controller has reached the error passive status at least one error counter exceeds the CAN protocol defined leve...

Page 325: ...to 28 0 0011 Start of frame 0 0100 Standard frame RTR bit 0 0101 IDE bit 0 0110 Reserved 0 0111 Identifier bits 13 to 17 0 1000 CRC sequence 0 1001 Reserved bit 0 0 1010 Data field 0 1011 Data length...

Page 326: ...it buffer status 3 is released transition from logic 0 to logic 1 0 9 TI2E R W Transmit interrupt enable 2 1 An interrupt is generated if the transmit buffer status 2 is released transition from logic...

Page 327: ...0 0 RIE R W Receive interrupt enable 1 An interrupt is generated if the receive buffer is not empty 0 Table 272 CAN controller interrupt enable register bit descriptioN CCIE address 0xE008 0010 CAN0...

Page 328: ...ment of the CCEWL register 13 to 10 reserved R Reserved do not modify Read as logic 0 9 to 0 BRP 9 0 R W Baud rate prescaler This derives the CAN clock tscl from the BASE_IVNSS_CLK branch clocks to th...

Page 329: ...has reached its limiting value of FFh 0 22 ES R Error status 1 One or both of the transmit and receive error counters has reached the limit set in the error warning limit register 0 21 TS3 R Transmit...

Page 330: ...ccessfully completed 0 The previously requested transmission from transmit buffer 2 is not yet completed 10 TBS2 2 R Transmit buffer status 2 1 Transmit buffer 2 is available for the CPU 0 Transmit bu...

Page 331: ...the limit set in the error warning limit register 0 5 TS1 R Transmit status 1 1 The CAN controller is transmitting a message from transmit buffer 1 4 RS R Receive status 1 The CAN controller is recei...

Page 332: ...rame format 1 An extended frame format message has been received 0 A standard frame format message has been received 30 RTR R Remote frame request 1 A remote frame has been received 0 A data frame has...

Page 333: ...t description CCRXBID address 0xE008 0024 CAN0 and 0xE008 1024 CAN1 reset value Bit Symbol Access Value Description 31 to 29 reserved R Reserved do not modify Read as logic 0 28 to 0 ID 28 0 R Identif...

Page 334: ...to 24 DB8 7 0 R Data byte 8 If the data length code value is eight or more this register contains the eighth data byte of the received message 00h 23 to 16 DB7 7 0 R Data byte 7 If the data length co...

Page 335: ...be transmitted if bit RTR is logic 0 or the requested number of data bytes if bit RTR is logic 1 Values greater than eight are handled as eight data bytes 0h 15 to 8 reserved R Reserved do not modify...

Page 336: ...8 1048 0xE008 1058 CAN1 reset value Bit Symbol Access Value Description 31 to 24 DB4 7 0 R W Data byte 4 If the data length code value is four or more this register contains the fourth data byte of th...

Page 337: ...ata B register bit description CCTX1 2 3DB addresses 0xE008 003C 0xE008 004C 0xE008 005C CAN0 and 0xE008 103C 0xE008 104C 0xE008 105C CAN1 continued reset value Bit Symbol Access Value Description Tab...

Page 338: ...d identifiers in the acceptance filter look up table Table 21 286 shows the bit assignment of the CASFGSA register Table 285 CAN acceptance filter standard frame explicit start address register bit de...

Page 339: ...to 12 reserved R Reserved do not modify Read as logic 0 11 to 2 SFGSA 9 0 R W Standard frame group start address This register defines the start address of the section of grouped standard identifiers...

Page 340: ...off modes Read access is possible in acceptance filter on and off modes The extended frame explicit start address is aligned on word boundaries and therefore the lowest two bits must be always logic...

Page 341: ...er Table 289 CAN acceptance filter end of look up table address register bit description CAEOTA address 0xE008 7014 reset value Bit Symbol Access Value Description 31 to 12 reserved R Reserved do not...

Page 342: ...ress register bit description CALUTEA address 0xE008 7018 reset value Bit Symbol Access Value Description 31 to 11 reserved R Reserved do not modify Read as logic 0 10 to 2 LUTEA 8 0 R Look up table e...

Page 343: ...ng bit x 0 31 IntPnd31 FullCan Interrupt Pending bit 31 0 Table 294 FullCAN Interrupt and Capture register 1 FCANIC1 address 0xE008 7028 bit description Bit Symbol Description Reset Value 0 IntPnd32 F...

Page 344: ...bus and error status of all the CAN controllers The status flags are the same as those in the status register of the corresponding CAN controller The CCCMS register is read only Table 21 297 shows the...

Page 345: ...so called FullCAN receive function This additional feature uses an internal message handler to move received FullCAN messages from the receive buffer of the according CAN controller into the FullCAN m...

Page 346: ...Register for IDs not handled in this way are increased by SFF_sa 2 compared to the values they would have when eFCAN is 0 When a Standard ID is received the Acceptance Filter searches this table befo...

Page 347: ...y therein If SEM 1 0 01 then the Acceptance Filter is currently active in this message object If SEM 1 0 11 then the message object is available to be read Before the CPU begins reading from the messa...

Page 348: ...ll rights reserved User manual Rev 00 06 17 December 2008 348 of 571 NXP Semiconductors UM10316 Chapter 21 LPC29xx CAN 0 1 Fig 77 Semaphore procedure for reading an auto stored message read 1st word S...

Page 349: ...s set the FullCAN Receive Interrupt is passed to the Vectored Interrupt Controller Application Software has to solve the following 1 Index Object number calculation based on the bit position in the FC...

Page 350: ...AN Source Channel SCC of the received FullCAN message is added to Message Object Fig 78 FullCAN section example of the ID look up table 0 FullCAN Explicit Standard Frame Format Identifier Section 11 b...

Page 351: ...e of an accepted FullCAN message and when the FullCAN Interrupt of the same object is asserted already During the first write access from the data storage of a FullCAN message object the Message Lost...

Page 352: ...ore a third message gets stored 3rd Object write Since the FullCAN Interrupt of that Object IntPndx is already asserted the Message Lost Signal gets asserted Fig 80 Normal case no messages lost 01 11...

Page 353: ...bject another new message gets stored by the message handler In this case the FullCAN Interrupt bit gets set for a second time with the 2nd Object write 11 3 4 Scenario 3 1 Message gets overwritten in...

Page 354: ...erwritten indicated by Message Lost This scenario is a sub case to Scenario 3 in which the lost message is indicated by Message Lost Fig 83 Message overwritten indicated by semaphore bits and message...

Page 355: ...d message object 2nd Object write The subsequent read out of that object by Software 1st Object read clears the pending Interrupt The 3rd Object write clears the Message Lost bit Every write ID SEM cl...

Page 356: ...ID look up table two CAN identifiers with their source CAN channels SCCs share one 32 bit word Unused or disabled CAN identifiers can be marked by setting the message disable bit To provide memory sp...

Page 357: ...bit in the upper and lower boundary identifiers To provide memory space for four Groups of standard frame format identifiers the CAEFESA register value is set to 20h The identifier group with Index 9...

Page 358: ...e 1 11 0 SCC 11 0 SCC 0 SCC 0 1 SCC 8 0 SCC 6 0 SCC 0 SCC 1 Explicit Standard Frame Format Identifier Section Group of Standard Frame Format Identifier Section CASFGSA 10h CASFESA 00h 2 0 SCC 3 0 SCC...

Page 359: ...e CASFESA register value is set to 10h Identifier index 1 of this section is not used and is therefore disabled 13 2 Explicit standard frame format section 11 bit CAN ID The start address of the expli...

Page 360: ...must be organized as a sorted list or table with the SCCs in ascending order and in conjunction with the CAN Identifier There is no exception for disabled identifiers The upper and lower bound in an...

Page 361: ...D D R A F T D R A F T D R A F T D R A F T D R A F T D R A F T D R A UM10316_0 NXP B V 2008 All rights reserved User manual Rev 00 06 17 December 2008 361 of 571 NXP Semiconductors UM10316 Chapter 21...

Page 362: ...LIN master The LIN master controller can send complete message frames without interrupting the CPU Generation of a new message frame is always initiated by a transmission request command This LIN mast...

Page 363: ...frame As soon as an error condition is detected the message frame is aborted at the end of the current field Error conditions are signaled either via the status register or by error interrupts 3 1 LI...

Page 364: ...ill be detected first for this field since the differences between the transmitted and received bits lead to this conclusion The LIN master aborts message transmission at the end of a field where a bi...

Page 365: ...ng error interrupt NRI is asserted as soon as the time out limit is exceeded 4 LIN register overview The LIN master controller registers are shown in Table 22 303 The LIN master controller registers h...

Page 366: ...5 shows the bit assignment of the LCFG register 2Ch R W 0000 0000h LDATA LIN master controller message buffer data A register see Table 22 314 30h R W 0000 0000h LDATB LIN master controller message bu...

Page 367: ...to send onto the LIN bus 6 SWCS R W Software checksum 1 Checksum is generated by software 0 Checksum is generated by hardware 5 reserved R Reserved do not modify Read as logic 0 4 and 3 IBS 1 0 R W In...

Page 368: ...LIN fCLK LIN divided by the divisor plus fraction value In LIN master controller mode this register is only writable in reset mode The baud rate can be calculated with the following formula Example Sy...

Page 369: ...ter The LIN master controller status register LSTAT reflects the status of the LIN master controller Figure 22 90 shows the status flag handling in terms of transmitting and receiving header and respo...

Page 370: ...The current TXD line level is recessive 8 RLL R RXD line level 1 The current RXD line level is dominant 0 The current RXD line level is recessive 7 reserved R Reserved read as logic 0 001aaa173 HS IS...

Page 371: ...error condition was detected 0 No errors have been detected The error status is cleared automatically when a new transmission is initiated 4 TS R Transmit status 1 The LIN master controller is transm...

Page 372: ...received slave responses 0111 Reserved 1000 Recessive line clamped error RXD TXD line stuck recessive 1001 Dominant line clamped error RXD TXD line stuck dominant 1010 Reserved 1111 Reserved 7 reserv...

Page 373: ...streams Violation of the configured inter byte space length A stop bit of fields from received slave responses was not recessive 0 1 TI R Transmit message complete interrupt 1 A complete LIN message...

Page 374: ...o the CPU as read write memory In this case and before a transmission is initiated the software has to provide the checksum to the checksum register Table 22 311 shows the bit assignment of the LCS re...

Page 375: ...similar length 2 Configure the time out condition prior to each LIN message applicable when the expected slave response length varies The time out period to be programmed can be calculated from the f...

Page 376: ...ication see Ref 32 6 4 10 LIN master controller message buffer registers Access to the message buffer is limited and controlled by the message buffer access bit of the status register Access to the LI...

Page 377: ...aster time out register is LTO 0000 001Ch Example 2 with eight data fields NData 8 in the expected slave response The value for this example of the LIN master time out register is LTO 0000 007Eh Table...

Page 378: ...identifier 00h Table 314 LDATA register bit description reset value Bit Symbol Access Value Description 31 to 24 DF4 7 0 R W LIN message data field 4 00h 23 to 16 DF3 7 0 R W LIN message data field 3...

Page 379: ...O pins for the desired LIN channels 2 Enter reset mode by setting the LRM bit of the LIN master controller mode register LMODE 3 Choose a baud rate by writing the appropriate value to the LIN master...

Page 380: ...er the data length code DLC and if required the message data to the LIN master message buffer The data direction bit DD is set to LOW Choose a slave not responding timeout condition and write the rela...

Page 381: ...rial transfer The I2C bus can be used for test and diagnostic purposes All I2C bus controllers support multiple address recognition and a bus monitor mode 3 Applications Interfaces to external I2C sta...

Page 382: ...pull up resistor must be disabled in the SFSPn_m register Table 6 58 The value of the external pull up resistor influences the rising edge of the SDA and SCL signals For low frequency applications 20...

Page 383: ...te bit Data is transmitted 8 bits at a time After each byte is transmitted an acknowledge bit is received START and STOP conditions are output to indicate the beginning and the end of a serial transfe...

Page 384: ...the Status Register will show the status code For master mode the possible status codes are 0x40 0x48 or 0x38 For slave mode the possible status codes are 0x68 0x78 or 0xB0 For details refer to Table...

Page 385: ...ndled as in the slave receiver mode However in this mode the direction bit will be 1 indicating a read operation Serial data is transmitted via SDA while the serial clock is input through SCL START an...

Page 386: ...d with the internal clock and spikes shorter than three clocks are filtered out The output for I2C is a special pad designed to conform to the I2C specification The outputs for I2C1 and I2C2 are stand...

Page 387: ...8 387 of 571 NXP Semiconductors UM10316 Chapter 23 LPC2xx I2C interface Fig 99 I2C Bus serial interface block diagram APB BUS STATUS REGISTER CONTROL REGISTER SCL DUTY CYCLE REGISTERS ADDRESS REGISTER...

Page 388: ...e last byte present on the bus Thus in the event of lost arbitration the transition from master transmitter to slave receiver is made with the correct data in I2DAT 7 5 Arbitration and synchronization...

Page 389: ...de It is switched off when the I2C block is in a slave mode The I2C output clock frequency and duty cycle is programmable via the I2C Clock Control Registers See the description of the I2CSCLL and I2C...

Page 390: ...routines see the software example in this section 8 Register description Each I2C interface contains 7 registers as shown in Table 23 322 below Table 322 I2C register map base address 0xE008 2000 I2C0...

Page 391: ...the general call address R W 0x00 I2C0ADR2 0xE0008 2024 I2C1ADR2 0xE0008 3024 I2ADR3 I2C Slave Address Register 3 Contains the 7 bit slave address for operation of the I2C interface in slave mode and...

Page 392: ...ay be set at any time including when the I2C interface is in an addressed slave mode STA can be cleared by writing 1 to the STAC bit in the I2CONCLR register When STA is 0 no START condition or repeat...

Page 393: ...the acknowledge clock pulse on the SCL line on the following situations 1 A data byte has been received while the I2C is in the master receiver mode 2 A data byte has been received while the I2C is in...

Page 394: ...and duty cycle I2SCLH defines the number of PCLK cycles for the SCL high time I2SCLL defines the number of PCLK cycles for the SCL low time The peripheral I2C clock PCLK is the base clock BASE_IVNSS_...

Page 395: ...of this register causes the corresponding bit in the I2C control register to be cleared Writing a zero has no effect AAC is the Assert Acknowledge Clear bit Writing a 1 to this bit clears the AA bit...

Page 396: ...2CMMCTRL0 0xE008 201C I2C1 I2C1MMCTRL 0xE008 301C bit description Bit Symbol Value Description Reset value 0 MM_EN A Monitor mode enable 0 0 Monitor mode disabled 1 The I2C module will enter monitor m...

Page 397: ...our module is concerned Software should be aware of the fact that the module is in monitor mode and should not respond to any loss of arbitration state that is detected In addition hardware may be de...

Page 398: ...ve bits 7 1 Any bit in these registers which is set to 1 will cause an automatic compare on the corresponding bit of the received address when it is compared to the I2ADDRn register associated with th...

Page 399: ...ed by software When a serial interrupt routine is entered the status code in I2STAT is used to branch to the appropriate service routine For each status code the required software action and details o...

Page 400: ...0x38 for the master mode and also 0x68 0x78 or 0xB0 if the slave mode was enabled AA logic 1 The appropriate action to be taken for each of these status codes is detailed in Table 23 339 After a repe...

Page 401: ...n slave address followed by the data direction bit which must be 0 W for the I2C block to operate in the slave receiver mode After its own slave address and the W bit have been received the serial int...

Page 402: ...entry MR MT to corresponding states in Slave mode A OR A A OR A A other Master continues other Master continues A other Master continues 20H 08H 18H 28H 30H 10H 68H 78H B0H 38H 38H arbitration lost in...

Page 403: ...to corresponding states in Slave mode A R SLA S R SLA S W A A OR A A P other Master continues other Master continues A other Master continues 48H 40H 58H 10H 68H 78H B0H 38H 38H arbitration lost in Sl...

Page 404: ...80H 88H reception of the General Call address and one or more Data bytes arbitration lost as Master and addressed as Slave last data byte received is Not acknowledged arbitration lost as Master and a...

Page 405: ...2 The slave transmitter mode may also be entered if arbitration is lost while the I2C block is in the master mode see state 0xB0 If the AA bit is reset during a transfer the I2C block will transmit th...

Page 406: ...x20 SLA W has been transmitted NOT ACK has been received Load data byte or 0 0 0 X Data byte will be transmitted ACK bit will be received No I2DAT action or 1 0 0 X Repeated START will be transmitted...

Page 407: ...action 1 0 0 X A START condition will be transmitted when the bus becomes free 0x40 SLA R has been transmitted ACK has been received No I2DAT action or 0 0 0 0 Data byte will be received NOT ACK bit w...

Page 408: ...r General call address has been received ACK has been returned No I2DAT action or X 0 0 0 Data byte will be received and NOT ACK will be returned No I2DAT action X 0 0 1 Data byte will be received and...

Page 409: ...addressed SLV mode Own SLA will be recognized General call address will be recognized if I2ADR 0 logic 1 A START condition will be transmitted when the bus becomes free 0xA0 A STOP condition or repeat...

Page 410: ...eceived 0xC0 Data byte in I2DAT has been transmitted NOT ACK has been received No I2DAT action or 0 0 0 0 Switched to not addressed SLV mode no recognition of own SLA or General call address No I2DAT...

Page 411: ...occurs between other states and when the I2C block is not involved in a serial transfer 23 9 5 2 I2STAT 0x00 This status code indicates that a bus error has occurred during an I2C serial transfer A bu...

Page 412: ...ter loss of arbitration Arbitration may be lost in the master transmitter and master receiver modes see Figure 23 100 Loss of arbitration is indicated by the following states in I2STAT 0x38 0x68 0x78...

Page 413: ...tional clock pulses when the STA flag is set but no START condition can be generated because the SDA line is pulled LOW while the I2C bus is considered free The I2C hardware attempts to generate a STA...

Page 414: ...block is enabled for both master and slave modes For each mode a buffer is used for transmission and reception The initialization routine performs the following functions I2ADR is loaded with the part...

Page 415: ...rating modes are not used the associated state services can be omitted as long as care is taken that the those states can never occur In an application it may be desirable to implement some kind of ti...

Page 416: ...10 5 1 State 0x00 Bus Error Enter not addressed Slave mode and release bus 1 Write 0x14 to I2CONSET to set the STO and AA bits 2 Write 0x08 to I2CONCLR to clear the SI flag 3 Exit 10 6 Master states S...

Page 417: ...crement Master Transmit buffer pointer 5 Exit 10 7 2 State 0x20 Slave Address Write has been transmitted NOT ACK has been received A Stop condition will be transmitted 1 Write 0x14 to I2CONSET to set...

Page 418: ...d and ACK returned 1 Write 0x04 to I2CONSET to set the AA bit 2 Write 0x08 to I2CONCLR to clear the SI flag 3 Exit 10 8 2 State 0x48 Slave Address Read has been transmitted NOT ACK has been received A...

Page 419: ...Arbitration has been lost in Slave Address and R W bit as bus Master Own Slave Address Write has been received ACK has been returned Data will be received and ACK will be returned STA is set to restar...

Page 420: ...er pointer 8 Exit 10 9 6 State 0x88 Previously addressed with own Slave Address Data has been received and NOT ACK has been returned Received data will not be saved Not addressed Slave mode is entered...

Page 421: ...pointer 6 Exit 10 10 2 State 0xB0 Arbitration lost in Slave Address and R W bit as bus Master Own Slave Address Read has been received ACK has been returned Data will be transmitted ACK bit will be r...

Page 422: ...T D R A UM10316_0 NXP B V 2008 All rights reserved User manual Rev 00 06 17 December 2008 422 of 571 NXP Semiconductors UM10316 Chapter 23 LPC2xx I2C interface 3 Exit 10 10 5 State 0xC8 The last data...

Page 423: ...ions A complete overview of the synchronization and trigger mechanism is shown in Figure 24 109 below 2 1 Synchronization and trigger features of the MSCSS The MSCSS contains two internal timers to ge...

Page 424: ...The match outputs of MSCSS timer 1 PWM control are connected to the corresponding carrier inputs of the PWM modules The carrier signal is modulated with the PWM generated waveforms The pause input of...

Page 425: ...eration on a configurable number of outputs 1 Timers c0 to c3 capture in 0 to capture in 3 m0 to m3 match out 0 to match out 3 2 ADCs st0 to st3 start 0 to start 3 inputs s0 to s3 sync_out 0 to sync_o...

Page 426: ...cond ADC with the sync_out of the first ADC but since sync_out is triggered on scan complete this is not the recommended method 3 2 Comparator functionality Since the ADC has a compare functionality i...

Page 427: ...ch output of MSCSS_Timer0 the trans_en_in and sync of PWM0 are triggered and the new pre loaded value for PWM0 is activated Pre loading new values into the registers can be done on the interrupts indi...

Page 428: ...ync delay output to trigger other PWM modules master slave behavior 3 Shadow registers and related update mechanism It is possible to reconfigure the PWM outputs on the fly changing frequency cycle pe...

Page 429: ...re 25 111 illustrates the operation of a PWM in continuous mode Each PWM consists of an internal 16 bit counter CNT register This counter is clocked with the prescaled system clock PRSC register When...

Page 430: ...generated when the internal PWM counter starts or restarts The signal TRANS_ENABLE_OUT is a pulse synchronous with SYNC_OUT but generated if a shadow register update occurs when the PWM counter restar...

Page 431: ...a negative and a positive transition at the corresponding external input pin Interrupts can be generated at each transition of the external capture input pin 4 5 Modulation of PWM and timer carrier Th...

Page 432: ...PWM output t t Timer1 output MSCSS timer0 resolution 1 s PWM in continuous mode sync_out activated sync_in and shadow register update triggered by SW Configure PWM0 output 0 disable trap enable carrie...

Page 433: ...PWM 3 output see Table 25 356 110h R W 0000 0000h MTCHACT 4 Holds the first activation match value related to PWM 4 output see Table 25 356 114h R W 0000 0000h MTCHACT 5 Holds the first activation ma...

Page 434: ...WM domain Stable only if TRANS_ENA is 0 see Table 25 366 900h R 0000 0000h MTCHACTS 0 Mirror the activation match shadowed value related to PWM 0 output see Table 25 367 904h R 0000 0000h MTCHACTS 1 M...

Page 435: ...0 93 F94h W INT_SET_ENABLE PWM interrupt set enable register see Table 10 94 F98h R 0000 0000h INT_STATUS PWM interrupt status register see Table 10 95 F9Ch R 0000 0000h INT_ENABLE PWM interrupt enabl...

Page 436: ...nable_in pin of the PWM If TRANS_ENA_SEL is cleared the trans_enable_in pin is ignored and update of the shadow registers takes place when the TRANS_ENA bit is set AND the PWM counter starts a new cyc...

Page 437: ...ycle 0 1 CNT_RESET R W 1 Synchronously reset PWM counter and prescale counter Counters remain reset when this bit is active 0 0 CNT_ENA R W 1 Enables the PWM counter and prescale counter 0 Table 347 B...

Page 438: ...elected between the external PWMx CAPTy and PWMx TRAP pins and the internal sync_in and the trans_enable_in signals Table 25 350 shows the bit assignment of the CAPSRC register Table 349 CAPCTL regist...

Page 439: ...s 1 PWM output period is PRD 1 PRSC 1 system clock cycles Given the desired PWM period values for PRD and PRSC can be derived from PRD PRSC tPWM tclk sys 1 1 and 0 CAPT_SRC0 1 0 R W Select the source...

Page 440: ...of the SYNDEL register 5 10 PWM count register The CNT register contains the current PWM value When the PRSC register is zero the PWM counter increments every system clock cycle when the PRSC register...

Page 441: ...match deactive registers There are six MTCHDEACT registers per PWM one for each PWM output Each MTCHACT register can be programmed to contain the second value which is compared to the PWM counter to g...

Page 442: ...on 25 5 1 for more information on the principle of shadow registers Table 25 359 shows the bit assignment of the MODECTLS register 5 15 PWM trap control shadow register The TRPCTLS register is the sha...

Page 443: ...ource shadow register The CAPTSRCS register is the shadow register of the CAPTSRC register It mirrors the values used in the PWM domain See Section 25 5 1 for more information about the principle of s...

Page 444: ...25 5 1 for more information on the principle of shadow registers Table 25 364 shows the bit assignment of the PRDS register Table 362 CAPTSRCS register bit description reset value Bit Symbol Access V...

Page 445: ...ows the bit assignment of the SYNDELS register 5 22 PWM match active shadow registers The MTCHACTS registers are the shadow registers of the MTCHACT registers They mirror the values used in the PWM do...

Page 446: ...outed to the Vectored Interrupt Controller VIC see Section 9 2 The interrupt process has a maximum of 19 possible sources 12 match events for intreq_capt_match 3 capture events for intreq_capt_match 1...

Page 447: ...lse Width Modulator PWM Table 370 PWM Match interrupt sources Register bit Interrupt source Description 31 to 12 unused Unused 11 MTCHDEACT5 PWM counter value matching MTCHDEACT5 6 MTCHDEACT0 PWM coun...

Page 448: ...are converted sequentially at each conversion scan The conversion can have a resolution of between two and 10 bits configurable per channel and it can be either a single or a continuous scan The conve...

Page 449: ...a programmable fractional system clock divider dedicated to the ADC clock to fulfill this constraint or to select the desired lower sampling frequency The conversion rate is determined by the ADC cloc...

Page 450: ...010h R W 0000h ACC4 ADC channel 4 configuration register see Table 26 373 014h R W 0000h ACC5 ADC channel 5 configuration register see Table 26 373 018h R W 0000h ACC6 ADC channel 6 configuration reg...

Page 451: ...134h R W 0000h COMP13 ADC channel 13 compare register see Table 26 374 138h R W 0000h COMP14 ADC channel 14 compare register see Table 26 374 13Ch R W 0000h COMP15 ADC channel 15 compare register see...

Page 452: ...nversion data register see Table 26 375 230h R 0000h ACD12 ADC channel 12 conversion data register see Table 26 375 234h R 0000h ACD13 ADC channel 13 conversion data register see Table 26 375 238h R 0...

Page 453: ...egister bit description ACC0 to 15 addresses 0xE00C 2000 to 0xE00C203C ADC0 0xE00C 3000 to 0xE00C303C ADC1 0xE00C 4000 to 0xE00C403C ADC2 reset value Bit Symbol Access Value Description 31 to 4 reserv...

Page 454: ...ter the ADC scan has finished See Table note 1 below Table 26 372 for the meaning of channel 9 to channel 15 for ADC1 and ADC2 Table 26 376 shows the bit assignment of the COMP_STATUS register 15 to 1...

Page 455: ...n is being done when set to 1 the ADC is never put into power down mode Bits 7 to 15 configure the enabling of the several start inputs per ADC start 0 to start 3 Setting to 1 enables the start When e...

Page 456: ...logic 0 15 NEGEDGE_START_3 R W 1 Enable ADC starting on the negative edge of start 3 The match output x of MSCSS timer 0 x is equal to ADC number 0 14 POSEDGE_START_3 R W 1 Enable ADC starting on the...

Page 457: ...ists of two bits The ADC_STATUS bit bit 0 this bit indicates whether an ADC scan is in progress bit is set to 1 or not bit is set to 0 When the configuration is set to internal trigger ADC_CONFIG 3 0...

Page 458: ...pt registers For a general explanation of the interrupt concept and a description of the registers see Section 10 6 Table 380 ADC_STATUS register bit description ADC_STATUS addresses 0xE00C 2408 ADC0...

Page 459: ...n counting Index compare register with interrupts Can combine index and position interrupts to produce an interrupt for whole and partial revolution displacement Digital filter with programmable delay...

Page 460: ...g 116 Encoder interface block diagram 002aad520 index Ph A Ph B BASE_MSCSS_CLK DIGITAL FILTER QUAD DECODER VELOCITY TIMER velocity interrupt TIM_Int low velocity interrupt LVEL_Int encoder clock inter...

Page 461: ...the SigMode bit of the QEI Control QEICON register See Table 27 387 When the SigMode bit 1 the quadrature decoder is bypassed and the PhA pin functions as the direction signal and PhB pin functions as...

Page 462: ...as output by some encoders The position counter is automatically reset on one of two conditions Incrementing past the maximum position value QEIMAXPOS will reset the position counter to zero If the re...

Page 463: ...vider of 1 VelDiv set to 0 and clocking on both PhA and PhB edges this results in 81 920 pulses per second the motor turns 10 times per second If the timer were clocked at 10 000 Hz and the loadvalue...

Page 464: ...S 0xE00C 900C R Position register QEIMAXPSOS 0xE00C 9010 R W Maximum position register CMPOS0 0xE00C 9014 R W position compare register 0 CMPOS1 0xE00C 9018 R W position compare register 1 CMPOS2 0xE0...

Page 465: ...counter on index When set 1 resets the the position counter to all zeros when an index pulse occurs Autoclears when the position counter is cleared 0 2 RESV Reset velocity When set 1 resets the the v...

Page 466: ...ter Interrupts can be enabled to interrupt when the compare value is less than equal to or greater than the current value of the position register 6 3 4 QEI Position Compare 1 CMPOS1 This register con...

Page 467: ...the current value of the velocity timer When this timer overflows the value of velocity counter QEIVEL is stored in the velocity capture register QEICAP the velocity counter is reset to zero the timer...

Page 468: ...city compare interrupt VELC_Int will be asserted if enabled 6 3 13 QEI Digital Filter FILTER This register contains the sampling count for the digital filter A sampling count of zero bypasses the filt...

Page 469: ...han compare velocity 0 3 DIR_Int Indicates that a change of direction was detected 0 4 ERR_Int Indicates that an encoder phase error was detected 0 5 ENCLK_Int Indicates that and encoder clock pulse w...

Page 470: ...an compare velocity 0 3 DIR_Int Indicates that a change of direction was detected 0 4 ERR_Int Indicates that an encoder phase error was detected 0 5 ENCLK_Int Indicates that and encoder clock pulse wa...

Page 471: ...y is less than compare velocity 0 3 DIR_Int Indicates that a change of direction was detected 0 4 ERR_Int Indicates that an encoder phase error was detected 0 5 ENCLK_Int Indicates that and encoder cl...

Page 472: ...an compare velocity 0 3 DIR_Int Indicates that a change of direction was detected 0 4 ERR_Int Indicates that an encoder phase error was detected 0 5 ENCLK_Int Indicates that and encoder clock pulse wa...

Page 473: ...ss than compare velocity 0 3 DIR_EN Indicates that a change of direction was detected 0 4 ERR_EN Indicates that an encoder phase error was detected 0 5 ENCLK_EN Indicates that and encoder clock pulse...

Page 474: ...s detected 0 4 ERR_EN Indicates that an encoder phase error was detected 0 5 ENCLK_EN Indicates that and encoder clock pulse was detected 0 6 POS0_Int Indicates that the position 0 compare value is eq...

Page 475: ...lash memory flash EEPROM and a controller the FMC to control access to both The EEPROM for the LPC29xx contains one 16 kB EEPROM block The controller can be accessed in two ways either by register acc...

Page 476: ...part that can be written at once is a flash word 16 bytes Table 28 410 lists the various parameters of the flash memory 2 2 Flash memory reading During a read e g read only data or program execution n...

Page 477: ...led again Protection is automatically enabled on a reset During a write erase burn operation the internal clock of the flash must be enabled After completion the clock can be disabled again In the fol...

Page 478: ...ark Like erasing a sector or burning a page the generation of a signature is also an asynchronous action i e after starting generation the module begins calculating the signature and during this proce...

Page 479: ...s Any interrupt service routine that needs to be serviced during this period must be stored entirely outside the flash memory e g in internal RAM Remark To detect the completion of an operation e g er...

Page 480: ...ow to disable ECC and unprotect the index sector unprotect index sector FMC_INX_SECTOR UNPROTECT FCTR FS_ISS FS_LOADREQ FS_WPB FS_WEB FS_WRE FS_CS FTCTR FTCTR 1 29 1 28 disable error correction re ena...

Page 481: ...x sector that defines whether it is secured or not Table 28 412 shows the link between index sector flash words and sectors in flash memory To protect a sector set the FS_ISS bit It is necessary to pr...

Page 482: ...m 8 bytes before the second operation which is called erase program in this document can be used to actually update the non volatile memory Note that the data written to the page register is not cache...

Page 483: ...m bus clock Next to this also the EEWSTATE needs to be programmed with wait state values After programming these registers operations on the EEPROM devices can be started 2 10 EEPROM operations An EEP...

Page 484: ...errupt status register to see if an operation is still pending before starting the write operation Polling is only sensible for systems running at a high frequency 200 MHz Software has to make sure th...

Page 485: ...is is a separate step writing only the page register will not write the EEPROM memory Programming the page into memory takes a long time therefore the corresponding interrupt can be enabled or the int...

Page 486: ...way the first read operation is started as result of writing the command register The following read operations are started as result of reading the read data register to obtain the result of the pre...

Page 487: ...able 28 418 014h R reserved Reserved register do not modify 018h R reserved Reserved register do not modify 01Ch R W 000h FCRA Flash clock divider register see Table 28 419 020h R W 0 0000h FMSSTART F...

Page 488: ...ys done without buffering with the programmed number of WSTs on every beat of the burst Index sector reading can be done both synchronously and asynchronously and is selected with the FS_ISS bit Table...

Page 489: ...eset value 13 FS_CACHEBYP R W Buffering bypass 1 Reading from flash memory is without buffering 0 Read buffering is active 12 FS_PROGREQ R W Programming request 1 Flash memory programming is requested...

Page 490: ...d erasing the flash memory It also allows reading of the remaining burn or erase time A built in timer is used to control the burn time or erase time The timer is started by writing the burn or erase...

Page 491: ...512 TR clock cycles 0000h Reset value ter twr pg 512 tclk sys Table 417 FTCTR FLASH test control register FTCTR address 0x2020 000C Bits Acce ss Reset value Field name Description 31 R W 0 FS_PARCEL...

Page 492: ...ynchronous reading 13 1 2 R W 0 FS_HVSS 1 0 FS_HVSS 1 0 selects which internal signal will be on pin DCM 000 enppsc 001 enpndc 010 enppdc 011 hvonn 100 hvonp 101 go 110 f_RY 111 reserved 11 R W 0 F_FA...

Page 493: ...cy divided by 3 FCRA 1 The programmed value must result in a CRA clock frequency of 66 kHz 20 Table 28 419 shows the bit assignment of the FCRA register Table 418 FBWST register bit description FBWST...

Page 494: ...the BIST start address register and the stop address to the BIST stop address register The BIST start and stop addresses must be flash memory word aligned and can be derived from the AHB byte addresse...

Page 495: ...chronous operations i e after initiating them it takes some time before they complete During this period access to the flash memory results in wait states Table 421 FMSSTOP register bit description FM...

Page 496: ...ark Access to flash memory is blocked during asynchronous operations and results in wait states Any interrupt service routine that needs to be serviced during this period must be stored entirely outsi...

Page 497: ...010 32 bit read 011 8 bit write 100 16 bit write 101 32 bit write 110 erase program page 111 reserved 3 R W 0x0 RDPREFETCH Read data pre fetch bit 0 do not pre fetch next read data as result of readi...

Page 498: ...is used to read data from memory If the post increment bit in the command register is set reading this register will start the next read operation from the incremented address location as side effect...

Page 499: ...re programming is not necessary when switching between the different operations NOTE the wait states in the register are minus 1 encoded Table 431 EEPROM wait state register bit description EEESTATE...

Page 500: ...ash EEPROM 3 14 EEPROM clock divider register The EEPROM device s require s a 375 kHz clock This clock is generated by dividing the system bus clock The clock divider register contains the division fa...

Page 501: ...o 3 17 EEPROM BIST stop address register The EEPROM BIST stop address register is used to program the stop address for the BIST and also to start the BIST During BIST the EEPROM devices are accessed w...

Page 502: ...fixed zero since only even addresses are allowed The width of this field depends on the number of EEPROM devices 1 EEPROM device x 13 8 MSB 0 CS and 6 LSB bits 29 x 1 0x0 reserved 30 R W 0x0 DEVSEL B...

Page 503: ...D R A F T D R A F T D R A F T D R A F T D R A F T D R A UM10316_0 NXP B V 2008 All rights reserved User manual Rev 00 06 17 December 2008 503 of 571 NXP Semiconductors UM10316 Chapter 28 LPC29xx Flash...

Page 504: ...ductors UM10316 Chapter 28 LPC29xx Flash EEPROM 4 1 1 Un protecting sectors A sector gets unprotected by writing an even value to its base address followed by writing the un protect trigger value to t...

Page 505: ...which is true for A single sector gets erased by writing any value to an address within that sector followed by writing the erase trigger value to the FCTR register Only unprotected sectors can be er...

Page 506: ...must be done by the AHB master that initiates the transfer The flash itself does not offer this feature Note that multiple partial writing is best done with ECC bypassed to avoid corruption of the ECC...

Page 507: ...the same procedure as normal burning see Section 28 4 1 6 except that the ISS bit is also set as FCTR trigger Data is loaded using the normal writing and loading procedure see Section 28 4 1 5 4 2 Al...

Page 508: ...egisters must be equal to reference signatures The algorithms to derive the reference signatures are given in Figure 28 129 and Figure 28 130 The 16 bit signature is derived from the uncorrected parit...

Page 509: ...atures is calculated from the 16 bit read data while the other signature is calculated from the eight parity bits belonging to the 16 bit data There are separate signatures for both data and parity bi...

Page 510: ...B V 2008 All rights reserved User manual Rev 00 06 17 December 2008 510 of 571 NXP Semiconductors UM10316 Chapter 28 LPC29xx Flash EEPROM Fig 132 Data bits BIST signature calculation sign 0 FOR addre...

Page 511: ...D R A F T D R A F T D R A F T D R A F T D R A F T D R A F T D R A UM10316_0 NXP B V 2008 All rights reserved User manual Rev 00 06 17 December 2008 511 of 571 1 How to read this chapter The contents...

Page 512: ...ize is set by programming the DMA Controller Memory to memory memory to peripheral peripheral to memory and peripheral to peripheral transfers are supported Scatter or gather DMA is supported through...

Page 513: ...ional port requires one stream for transmit and one for receive The source and destination areas can each be either a memory region or a peripheral and can be accessed through the AHB master Figure 30...

Page 514: ...aits until the transaction can complete Locked transfers for source and destination of each stream Setting of protection bits for transfers on each stream 4 1 6 1 Bus and transfer widths The physical...

Page 515: ...tle Little 8 16 1 7 0 2 15 8 3 23 16 4 31 24 21 43 65 87 1 15 0 2 31 16 43214321 87658765 Little Little 8 32 1 7 0 2 15 8 3 23 16 4 31 24 21 43 65 87 1 31 0 87654321 Little Little 16 8 1 7 0 1 15 8 2...

Page 516: ...asked Big Big 8 16 1 31 24 2 23 16 3 15 8 4 7 0 12 34 56 78 1 15 0 2 31 16 12341234 56785678 Big Big 8 32 1 31 24 2 23 16 3 15 8 4 7 0 12 34 56 78 1 31 0 12345678 Big Big 16 8 1 31 24 1 23 16 2 15 8 2...

Page 517: ...er interface by the lower priority channel before switching over to transfer data for the higher priority channel In the worst case this is as large as a one quadword It is recommended that memory to...

Page 518: ...sferred The DMA response signals from the DMA controller are DMACCLR 15 0 DMA clear or acknowledge signals The DMACCLR signal is used by the DMA controller to acknowledge a DMA request from the periph...

Page 519: ...R W Channel 2 registers 0xE014 0140 DMACC2SrcAddr DMA Channel 2 Source Address Register 0 R W 0xE014 0144 DMACC2DestAddr DMA Channel 2 Destination Address Register 0 R W 0xE014 0148 DMACC2LLI DMA Cha...

Page 520: ...ddr DMA Channel 6 Destination Address Register 0 R W 0xE014 01C8 DMACC6LLI DMA Channel 6 Linked List Item Register 0 R W 0xE014 01CC DMACC6Control DMA Channel 6 Control Register 0 R W 0xE014 01D0 DMAC...

Page 521: ...LOW have no effect on the corresponding bit in the register Table 30 450 shows the bit assignments of the DMACIntErrClr Register 5 6 DMA Raw Interrupt Terminal Count Status Register DMACRawIntTCStat 0...

Page 522: ...s read write and enables DMA burst requests to be generated by software A DMA request can be generated for each source by writing a 1 to the corresponding register bit A register bit is cleared when t...

Page 523: ...y writing a 1 to the corresponding register bit A register bit is cleared when the transaction has completed Reading the register indicates which sources are requesting last burst DMA transfers A requ...

Page 524: ...e is set to little endian mode on reset Table 30 458 shows the bit assignments of the DMACConfig Register 5 14 DMA Synchronization Register DMACSync 0xE014 0034 The DMACSync Register is read write and...

Page 525: ...ata has been transferred Reading the register when the channel is active does not provide useful information This is because by the time software has processed the value read the address may have prog...

Page 526: ...ntrol 0xE014 01xC The eight read write DMACCxControl Registers DMACC0Control to DMACC7Control contain DMA channel control information such as the transfer size burst size and transfer width Each regis...

Page 527: ...stination increment 0 the destination address is not incremented after each transfer 1 the destination address is incremented after each transfer 26 SI Source increment 0 the source address is not inc...

Page 528: ...ctive in the destination peripheral 000 1 001 4 010 8 011 16 100 32 101 64 110 128 111 256 14 12 SBSize Source burst size Indicates the number of transfers that make up a source burst This value must...

Page 529: ...nsfer type can be memory to memory memory to peripheral peripheral to memory or peripheral to peripheral Refer to Table 30 465 for the encoding of this field 10 6 DestPeripheral Destination peripheral...

Page 530: ...rol and transfer type Table 30 465 lists the bit values of the three flow control and transfer type bits identified in Table 30 464 6 Using the DMA controller 6 1 Programming the DMA controller All ac...

Page 531: ...register until it reaches 0 This bit indicates whether there is any data in the channel that has to be transferred Clear the channel enable bit in the relevant channel configuration register 6 1 5 Se...

Page 532: ...r size value in the DMACCxControl register is ignored if a peripheral is configured as the flow controller When the DMA transfer is completed 1 The DMA Controller issues an acknowledge to the peripher...

Page 533: ...nt interrupt is generated this interrupt can be masked If the DMACCxLLI Register is not 0 then reload the DMACCxSrcAddr DMACCxDestAddr DMACCxLLI and DMACCxControl registers and go to back to step 2 Ho...

Page 534: ...nt the transfer count 5 If the count has reached zero Generate a terminal count interrupt the interrupt can be masked If the DMACCxLLI Register is not 0 then reload the DMACCxSrcAddr DMACCxDestAddr DM...

Page 535: ...ed with the specified burst size For example if the channel is set for 16 transfer burst to a 32 bit wide device then the boundary is 64 bytes aligned that is address bits 5 0 equal 0 If a DMA burst i...

Page 536: ...estination address Pointer to next LLI Control word The last LLI has its linked list word pointer set to 0 2 Choose a free DMA channel with the priority required DMA channel 0 has the highest priority...

Page 537: ...izes 16 transfers Next LLI address 0x20010 The second LLI stored at 0x20010 describes the next block of data to be transferred Source start address 0x0B200 Destination address set to the destination p...

Page 538: ...reserved User manual Rev 00 06 17 December 2008 538 of 571 NXP Semiconductors UM10316 Chapter 30 LPC29xx General Purpose DMA GPDMA controller Because the next LLI address is set to zero this is the la...

Page 539: ...main AMBA system bus It compresses the trace information and exports it to a trace buffer An internal Embedded Trace Buffer captures the trace information under software debugger control ETM can broad...

Page 540: ...refer to ARM documentation Embedded Trace Macrocell Specification ARM IHI 0014E 4 2 ETB configuration The ETB has a 2048 24 bit RAM for instruction data history storage 5 Block diagram Table 467 ETM c...

Page 541: ...M10316_0 NXP B V 2008 All rights reserved User manual Rev 00 06 17 December 2008 541 of 571 NXP Semiconductors UM10316 Chapter 31 LPC29xx ETM ETB interface 6 Register description 6 1 ETM registers Ple...

Page 542: ...n Language CAN Controller Area Network see Ref 32 5 CPU Central Processing Unit EC Motor Electronically Commutated Motor FIFO First In First Out FIQ Fast Interrupt FMC Flash Memory Controller GPIO Gen...

Page 543: ...unit to support debugging the ARM core via the JTAG interface in ARM debug mode see Ref 32 2 ER Event Router routes wake up events and external interrupts to CGU VIC FIFO First In First Out queuing b...

Page 544: ...d 1149 1 IEEE Standard Test Access Port and Boundary Scan Architecture 5 ISO 11898 1 2002 Road vehicles Controller area network CAN Part 1 Data link layer and physical signalling 6 LIN Specification P...

Page 545: ...he right to make changes to information published in this document including without limitation specifications and product descriptions at any time and without notice This document supersedes and repl...

Page 546: ...T D R A F T D R A F T D R A F T D R A F T D D R A F T D R A F T D R A F T D R A F T D R A F T D R A F T D R A UM10316_0 NXP B V 2008 All rights reserved User manual Rev 00 06 17 December 2008 546 of 5...

Page 547: ...scription PLL_CONTROL address 0xFFFF 8028 CGU0 and 0xFFFF B028 CGU1 47 Table 28 FDIV_STATUS_n register bit description FDIV_STATUS_0 to 6 address 0xFFFF 802C 34 3C 44 4C 54 5C CGU0 and FDIV_STATUS_0 a...

Page 548: ..._m register bit description base address 0xE000 1000 port 0 0xE000 1100 port 1 0xE000 1200 port 2 0xE000 1300 port3 0xE000 1400 port4 0xE000 1500 port 5 83 Table 66 SFSP5_16 function select register b...

Page 549: ...0x6000 0030 0x6000 004C 0x6000 0068 0x6000 0084 0x6000 00A0 0x6000 00BC 0x6000 00D8 150 Table 112 SMBSRn register bit description SMBSR0 toSMBSR7 addresses 0x6000 0018 0x6000 0034 0x6000 0050 0x6000...

Page 550: ...description 176 Table 155 USB UDCA Head register USBUDCAH address 0xE010 C280 bit description 176 Table 156 USB EP DMA Status register USBEpDMASt address 0xE010 C284 bit description 177 Table 157 USB...

Page 551: ...244 Table 203 DR register bit description DR0 to 5 addresses 0xE004 A008 GPIO0 0xE004 B008 GPIO1 0xE004 C008 GPIO2 0xE004 D008 GPIO3 0xE004 E008 GPIO4 0xE004 F008 GPIO5 245 Table 204 Timer register ov...

Page 552: ...d Only bit description 284 Table 242 UARTn Scratch Pad Register U0SCR address 0xE004 501C U1SCR 0xE004 601C bit description 284 Table 243 UARTn Auto baud Control Register U0ACR 0xE004 5020 U1ACR 0xE00...

Page 553: ...bit description CCTX1 2 3DB addresses 0xE008 003C 0xE008 004C 0xE008 005C CAN0 and 0xE008 103C 0xE008 104C 0xE008 105C CAN1 336 Table 284 CAN acceptance filter mode register bit description CAMODE ad...

Page 554: ...I2C0 I2CDATA_BUFFER 0xE008 202C I2C1 I2C1DATA_BUFFER 0xE008 302C bit description 398 Table 333 I2C Slave Address registers I2ADR0 to 3 I2C0 I2C0ADR 0 1 2 3 0xE008 20 0C 20 24 28 I2C1 I2C1ADR 0 1 2 3 a...

Page 555: ...465 Table 389 QEI Interrupt Status Register QEISTAT 0xE00C 9004 465 Table 390 QEI Position Register QEIPOS 0xE00C 900C 466 Table 391 QEI Maximum Position Register QEIMAXPOS 0xE00C 9010 466 Table 392...

Page 556: ...le 439 Automatic load trigger 505 Table 440 manual load trigger 505 Table 441 Burn trigger value 506 Table 442 Endian behavior 514 Table 443 Peripheral connections to the DMA controller and matching f...

Page 557: ...ks with 16 bit devices 141 Fig 37 External memory interface 8 bit banks with 8 bit devices 142 Fig 38 Reading from external memory 142 Fig 39 Writing to external memory 143 Fig 40 Reading writing exte...

Page 558: ...ronization 389 Fig 102 Format and States in the Master Transmitter mode 402 Fig 103 Format and States in the Master Receiver mode 403 Fig 104 Format and States in the Slave Receiver mode 404 Fig 105 F...

Page 559: ...Power driver functional description 24 4 Reset and power up behavior 24 5 Functional description of the interrupt and wake up structure 24 6 Interrupt device architecture 25 6 1 Interrupt registers 2...

Page 560: ...ipherals activated by cold reset 67 Peripherals activated by warm reset 67 4 5 RGU bus disable register 68 Chapter 6 LPC29xx Power Management Unit PMU 1 How to read this chapter 69 2 Introduction 69 3...

Page 561: ...ycle control registers 146 4 2 Bank wait state 1 control registers 147 4 3 Bank wait state 2 control registers 147 4 4 Bank output enable assertion delay control register 148 4 5 Bank write enable ass...

Page 562: ...BUDCAH 0xE010 C280 176 9 7 5 USB EP DMA Status register USBEpDMASt 0xE010 C284 176 9 7 6 USB EP DMA Enable register USBEpDMAEn 0xE010 C288 177 9 7 7 USB EP DMA Disable register USBEpDMADis 0xE010 C28C...

Page 563: ...3 Transferring the data 201 14 5 4 Optimizing descriptor fetch 201 14 5 5 Ending the packet transfer 201 14 5 6 No_Packet DD 202 14 6 Isochronous endpoint operation 202 14 6 1 Setting up DMA transfer...

Page 564: ...t signals 238 8 2 Clocking and power management 239 8 2 1 Device clock request signals 240 8 2 1 1 Host clock request signals 241 8 2 2 Power down mode support 241 9 USB OTG controller initialization...

Page 565: ...T0 RS485 Control register 291 4 16 UART0 RS485 Address Match register 292 4 17 UART1 RS 485 Delay value register 292 4 18 RS 485 modes of operation 292 RS 485 Normal Multidrop Mode NMM 292 RS 485 Auto...

Page 566: ...end of look up table address register 341 10 7 CAN acceptance filter look up table error address register 341 10 8 CAN acceptance filter look up table error register 342 10 9 Global FullCANInterrupt E...

Page 567: ...DDR 388 7 3 Comparator 388 7 4 Shift register I2DAT 388 7 5 Arbitration and synchronization logic 388 7 6 Serial clock generator 389 7 7 Timing and control 389 7 8 Control register I2CONSET and I2CONC...

Page 568: ...10 2 State 0xB0 421 10 10 3 State 0xB8 421 10 10 4 State 0xC0 421 10 10 5 State 0xC8 422 Chapter 24 LPC29xx Modulation and Sampling Control Subsystem MSCSS 1 How to read this chapter 423 2 MSCSS func...

Page 569: ...y 464 6 2 Control registers 465 6 2 1 QEI Control QEICON 465 6 2 2 QEI Configuration QEICONF 465 6 2 3 QEI Status QEISTAT 465 6 3 Position index and timer registers 466 6 3 1 QEI Position QEIPOS 466 6...

Page 570: ...8 Chapter 29 LPC29xx Flash and EEPROM JTAG programming 1 How to read this chapter 510 Chapter 30 LPC29xx General Purpose DMA GPDMA controller 1 How to read this chapter 511 2 Introduction 511 3 Featur...

Page 571: ...the DMA controller 529 6 1 Programming the DMA controller 529 6 1 1 Enabling the DMA controller 529 6 1 2 Disabling the DMA controller 529 6 1 3 Enabling a DMA channel 529 6 1 4 Disabling a DMA chann...

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