NXP Semiconductors LPC29 Series, User Manual

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UM10316_0 © NXP B.V. 2008. All rights reserved.
User manual Rev. 00.06 — 17 December 2008 23 of 571
1. How to read this chapter
This chapter describes the base clock generation for all LPC29xx parts.
2. Introduction
The CGU0 is part of the Power Control, Clock, and Reset control (PCR) block and
provides the clocks for all subsystems. A second, dedicated CGU1 provides the clocks for
the USB block and a clock output. The CGU1 has two clock inputs to its PLL which are
internally connected to two base clocks in the CGU0.
Both CGUs are functionally identical and have their own PLL and fractional divider
registers.
UM10316
Chapter 3: LPC29xx Clock Generation Unit (CGU)
Rev. 00.06 — 17 December 2008 User manual
Table 10. LPC29xx base clock options
Part CGU0 base clocks CGU1 base clocks
LPC2917/19/01 see Table 3–11 CLK_OUT
LPC2921/23/25 see Table 3–11 CLK_OUT, USB_CLK
LPC2927/29 see Table 3–11 CLK_OUT, USB_CLK, USB_INT_CLK
LPC2939 see Table 3–11 CLK_OUT, USB_CLK, USB_INT_CLK
LPC2930 see Table 3–11 CLK_OUT, USB_CLK, USB_INT_CLK