UM10208_2
© NXP B.V. 2007. All rights reserved.
User manual
Rev. 02 — 1 June 2007
82 of 362
NXP Semiconductors
UM10208
Chapter 7: LPC2800 CGU
Bit 4 (PERF_ANAL_ENA) of this register controls the cache performance analysis
counters in the registers C_RD_MISSES, C_FLUSHES, and C_WR_MISSES.
Performance analysis should be disabled when not needed in order to save power.
2.
CPU Clock Gate Control register (CPU_CLK_GATE - address 0x8010 4058):
Bit 0 (CPU_CLK_GATE) controls clock gating to the CPU. When clock gating is
enabled, power is saved by not clocking the CPU when it is stalled waiting for bus
access.
Flash interface and programming
Flash Power Down register (FLASH_PD - address 0x8000 5030):
Bit 0 (FLASH_PD) of the Flash Power Down register (FLASH_PD - 0x80005030) allows
shutting down the flash memory system in order to save power if it is not needed.
External memory controller
1.
EMC Control register (EMCControl - address 0x8000 8000):
If the EMC is unused, then the application could clear bit 0 (MPMC Enable) of this
register to disable the EMC, when the EMC is in idle state. Disabling the EMC
reduces power consumption.
2.
Dynamic Control register (EMCDynamicControl - address 0x8000 8020):
A 0 in bit 1 (Force CLKOUT) of this register saves power by stopping CLKOUT when
there are no SDRAM transactions and during self-refresh mode.
3.
Static Memory Configuration registers:
A one in the bit 19 (Write buffer Enable) of the Static Memory Configuration registers
enables the write buffers, which reduces external memory traffic. This improves
memory bandwidth and reduces power consumption.
Real-time clock
RTC Configuration register (RTC_CFG - address 0x8000 5024):
When the bit 0 (PWR_UP) of this register is 0, all bus interface inputs are gated. Besides
the first element in the ripple counter, and the optional alarm clock sampling flip flop, all
loads to the 32.768 kHz clock are gated to reduce power. However, the application must
always write a 1 to this bit before it can access any of the other registers in the RTC.
Analog-to-digital converter
1.
A/D Control register (ADCCON - 0x80002420):
A zero in the bit 1 (ADCENAB) of this register disables the digital portion of the ADC.
2.
A/D Power Down register (ADCPD - 0x80005028):
A one in the bit 0 (ADCPD) of this register removes power from the analog A/D circuit.
USB controller
USB Clock Enable register (USBClkEn - 0x80005050):
A one in the bit 0 (CLKEN) of this register enables the clock to the USB controller. The
application can write a 0 to this bit, to save power if the USB is not used.
