UM10208_2
© NXP B.V. 2007. All rights reserved.
User manual
Rev. 02 — 1 June 2007
76 of 362
NXP Semiconductors
UM10208
Chapter 7: LPC2800 CGU
5/12 of the SYS base clock by the fractional divider (SYSFDCR1), i.e. 25 MHz. The
LCD_CLK (LCD bus clock for LCD interface) is programmed as 1/10 of the SYS base
clock by the fractional divider (SYSFDCR3), i.e. 6 MHz.
Code example
#include <lpc288x.h>
#define CGU_FSR_MAIN_PLL 0x8
#define CGU_FSR1 0x1
#define CGU_FSR2 0x2
#define CGU_FDCR_FDRUN 0x1
#define CGU_FDCR_FDRES 0x2
#define CGU_FDCR_FDSTRCH 0x4
#define SYSFDCR1_MSUB 0xB0
#define SYSFDCR1_MADD 0x70
#define SYSFDCR3_MSUB 0xF0
#define SYSFDCR3_MADD 0x90
#define CGU_ESR_FD1 0x3
#define CGU_ESR_FD3 0x7
#define CGU_BCR_FDRUN 0x1
/*********************** Main PLL Setup***************************/
LPPDN = 0x00000001; /* Power down the main PLL */
LPFIN = 0x00000001; /* Select main oscillator as PLL's input clock */
LPMSEL = 0x00000004; /* Multiply input clock by (4 + 1) = 5 */
LPPSEL = 0x00000001; /* Make CCO equal to 4 times PLL output */
LPPDN = 0x00000000; /* Power up the main PLL */
while (LPLOCK == 0x00000000) {}; /* Wait for PLL to lock */
/*********************** Selection Stage ***************************/
if (SYSSSR & CGU_FSR1) {
SYSFSR2 = CGU_FSR_MAIN_PLL; /* Select Main PLL as main clock */
SYSSCR = (SYSSCR & 0xC) | CGU_FSR2; /* Enable side 2 */
} else {
SYSFSR1 = CGU_FSR_MAIN_PLL; /* Select Main PLL as main clock */
SYSSCR = (SYSSCR & 0xC) | CGU_FSR1; /* Enable side 1 */
}
/*********************** Programming the Fractional Divider registers ***************************/
/* Setup SYS Fractional Divider #1 for MCI_MCLK, MCI clock of SD/MCI interface */
/* MCI_MCLK, MCI clock of SD/MCI interface = (5/12) * SYS base clock */
SYSFDCR1 &= ~CGU_FDCR_FDRUN; /* Stop the fractional divider */
SYSFDCR1 = ((SYSFDCR1_MSUB << 11) /* Set MSUB = -n */
| (SYSFDCR1_MADD << 3) /* Set MADD = m - n */
| CGU_FDCR_FDSTRCH /* Enable stretch */
| CGU_FDCR_FDRES); /* Reset fractional divider */
SYSFDCR1 &= ~CGU_FDCR_FDRES; /* Clear reset bit */
SYSFDCR1 |= CGU_FDCR_FDRUN; /* Restart the fractional divider */
/* Setup SYS Fractional Divider #3 for LCD_CLK, LCD bus clock of LCD interface */
