UM10208_2
© NXP B.V. 2007. All rights reserved.
User manual
Rev. 02 — 1 June 2007
310 of 362
NXP Semiconductors
UM10208
Chapter 24: LPC2800 LCD
1. f(LCD clock)
≤
0.5
×
f(PCLK)
2. Remote device minimum write cycle
≤
5
×
LCD clock cycle
3. Remote device read access time (max)
≤
(2
×
LCD clock cycle) - LD7:0 setup Min
5.3 Setting the control register
If there is only a single remote device, the Control register can be written with the values
appropriate for that device, once during system initialization. In an application involving
more than one remote device, wait at least 7 LCD clocks after writing to LCDIBYTE or
LCDDBYTE, and at least 22 LCD clocks after writing to LCDIWORD or LCDDWORD,
before changing the control register to the configuration for a different device.
5.4 Writing to a Remote Device
Regardless of whether the interface is 8-bit, 4-bit, or serial mode, simply write to the
appropriate register among LCDIBYTE, LCDDBYTE, LCDIWORD, or LCDDWORD. If the
interface was in read mode, it is immediately changed back to write mode. If the output
FIFO was too full to accept the amount of data written, bit 2 of LCDISTAT (and LCDSTAT
if not masked) is set, and no data is written to the FIFO.
5.5 Reading from a Remote Device
1. If an interrupt is desired when the read operation is complete, clear bit 3 in the
LCDIMASK register if it’s not already 0, to enable such an interrupt.
2. Write to the LCDREAD register. Write 0 to read the “instruction register” with LRS low,
write 1 to read the “data register” with LRS high.
3. Wait for an interrupt with bit 3 of LCDSTAT set, or poll the LCDISTAT register until bit
3 is 1.
4. Read LCDIBYTE or LCDDBYTE to get the data from the remote device. (It doesn’t
matter which.)
5. If interrupt was used, write LCDICLR with bit 3 set, to clear the interrupt request,
before dismissing the interrupt.
5.6 Busy checking
If the LCDCBSY bit in the Control register is 1, before writing an instruction or data byte to
the external device, and before reading from the “data register” that’s selected by the
opposite state of LRS from that indicated by the LRSSEL bit in the Control register, the
LCD interface first reads the status register that’s selected by the state of LRS indicated in
LRSSEL, repeatedly if necessary, until the data bit selected by the LCDBSYN field in the
Control register has the state indicated by the CBSENSE bit in the Control register.
If CBUSY is set, and software writes to the LCDREAD register with the value that
commands reading with the same LRS state indicated by LRSSEL (that is, if software
commands reading the status register), the LCD interface simply reads the register once,
and does not wait for “not busy” status.
