UM10208_2
© NXP B.V. 2007. All rights reserved.
User manual
Rev. 02 — 1 June 2007
212 of 362
NXP Semiconductors
UM10208
Chapter 17: LPC2800 USB Device
interrupt. The length of the data packets transferred is equal to the MaxPacketSize
defined for the corresponding endpoint, except for the last packet. The last packet will be
communicated from the DMA engine to the USB core through the ‘end_of _transfer’
signal.
7.
Endpoint configuration
8.
Registers
This section describes the USB and USB DMA registers and provides programming
details.
8.1 USB controller register resetting
Registers in the USB Controller are affected by two kinds of resets: master reset and bus
reset. Master reset includes power-on reset and Watchdog reset. A bus reset is a unique
state of the USB D+ and D- lines (both low for 3 ms), which a host will assert at the start of
connecting a device to the USB. Since some register bits are affected differently by the
two kinds of reset, the following tables that describe particular registers contain “Master
Reset State” and “Bus Reset State” columns. An “NC” in the latter column means that a
bus reset doesn’t change the state of the bit.
8.2 USB controller register map
USB Controller registers are located as shown in
.
Table 232. Endpoint configuration
Logical endpoint
Physical endpoint
Direction
DMA channel
0
0
Out
No
0
1
In
No
1
2
Out
0/1
1
3
In
0/1
2
4
Out
0/1
2
5
In
0/1
3
6
Out
No
3
7
In
No
4
8
Out
No
4
9
In
No
5
10
Out
No
5
11
In
No
6
12
Out
No
6
13
In
No
7
14
Out
No
7
15
In
No
