UM10208_2
© NXP B.V. 2007. All rights reserved.
User manual
Rev. 02 — 1 June 2007
159 of 362
NXP Semiconductors
UM10208
Chapter 14: LPC2800 UART
3.7 FIFO Control Register (FCR - 0x8010 1008)
The write-only FCR controls the operation of the Rx and Tx FIFOs.
Table 174. FIFO Control Register (FCR - 0x8010 1008)
Bit
Name
Value Description
Reset
value
0
FIFO Enable 0
Both FIFOs are disabled (’450 mode)
0
1
Enables both the Rx and Tx FIFOs. Any transition on this bit
will automatically clear the FIFOs. If this bit is 0, the other bits
in this register will retain their old value.
1
Rx FIFO
Reset
0
No impact on either FIFO.
0
1
Writing a 1 to FCR[1] clears all bytes in the Rx FIFO and
resets the pointer logic. This bit always reads as 0.
2
Tx FIFO
Reset
0
No impact on either FIFO.
0
1
Writing a 1 to FCR[2] clears all bytes in the Tx FIFO and
resets the pointer logic. This bit always reads as 0.
3
DMAMode
If the FIFO Enable (FCR0) is 1 and the SDMA facility is used
to transfer data to or from the UART, this bit controls when
DMA transfers are requested:
0
0
Rx DMA is requested when the Rx FIFO is not empty. Tx DMA
is requested when the Tx FIFO is empty.
1
Rx DMA is requested when the Rx Trigger level (in FCR7:6) is
reached, or a timeout occurs, and is maintained until the Rx
FIFO is empty. Tx DMA is requested when the Tx FIFO is not
full.
5:4
-
-
Reserved, user software should not write ones to reserved
bits.
-
7:6
Rx Trigger
Level
This field determines how many characters must be in the Rx
FIFO before interrupt (or DMA transfer) is requested.
00
00
1 character
01
16 characters
10
24 characters
11
28 characters
31:8 -
Reserved, user software should not write ones to reserved
bits.
-
