UM10208_2
© NXP B.V. 2007. All rights reserved.
User manual
Rev. 02 — 1 June 2007
132 of 362
NXP Semiconductors
UM10208
Chapter 11: LPC2800 WDT
4.2 Watchdog Timer Control Register (WDT_TCR - 0x8000 2804)
The WDT_TCR controls whether the Timer Counter is enabled or cleared.
4.3 Watchdog Timer Counter Register (WDT_TC - 0x8000 2808)
The current value of the Timer Counter can be read from this register. While this register
can be written, writing is neither necessary nor recommended for Watchdog operation.
4.4 Watchdog Prescale Register (WDT_PR - 0x8000 280C)
When the value in the Prescale Counter matches the value in this register (and the
WDT_TCR enables counting), the Timer Counter is incremented and the Prescale
Counter is cleared at the next edge of the WDT clock. Thus, the Time Counter is
incremented by "the WDT clock divided by (the value in this register plus one)".
Table 131. Watchdog Timer Control Register (WDT_TCR - 0x8000 2804)
Bit
Function
Description
Reset
value
0
Counter
Enable
When this bit is 1, the Prescale Counter and Timer Counter are
enabled to count in response to WDT clocks from the CGU.
When it is 0 both counters are disabled.
0
1
Counter
Reset
When this bit is 1, the Prescale Counter and Timer Counter are
cleared at the next WDT clock edge from the CGU.
Write a 1 to
this bit on a regular basis, to prevent Watchdog reset and/or
interrupt.
Both counters remain cleared until this bit is 0, so write
a 0 to this bit immediately after writing a 1. The WDT clock must
be fast enough to guarantee an edge between the two write
operations, or the counters will not be cleared.
0
31:2
-
Reserved, user software should not write ones to reserved bits.
The value read from a reserved bit is not defined.
-
Table 132: Watchdog Timer Counter Register (WDT_TC - 0x8000 2808)
Bit
Function
Description
Reset Value
31:0
Timer Counter value
0
Table 133: Watchdog Prescale Register (WDT_PR - 0x8000 280C)
Bit
Function
Description
Reset Value
31:0
Prescaler limit value
0
