NXP Semiconductors LPC1751, User Manual, Page: 561 / 808

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UM10360_0 © NXP B.V. 2009. All rights reserved.
User manual Rev. 00.06 — 5 June 2009 561 of 808
1. Basic configuration
The GPDMA is configured using the following registers:
1. Power: In the PCONP register ( Table 4–46 ), set bit PCGPDMA.
Remark: On reset, the GPDMA is disabled (PCGPDMA = 0).
2. Clock: see Table 4–37 .
3. Interrupts: Interrupts are enabled in the NVIC using the appropriate Interrupt Set
Enable register.
4. Programming: see Section 31–6 .
2. Introduction
The DMA controller allows peripheral-to memory, memory-to-peripheral,
peripheral-to-peripheral, and memory-to-memory transactions. Each DMA stream
provides unidirectional serial DMA transfers for a single source and destination. For
example, a bi-directional port requires one stream for transmit and one for receives. The
source and destination areas can each be either a memory region or a peripheral.
3. Features
•
Eight DMA channels. Each channel can support an unidirectional transfer.
•
16 DMA request lines.
•
Single DMA and burst DMA request signals. Each peripheral connected to the DMA
Controller can assert either a burst DMA request or a single DMA request. The DMA
burst size is set by programming the DMA Controller.
•
Memory-to-memory, memory-to-peripheral, peripheral-to-memory, and
peripheral-to-peripheral transfers are supported.
•
GPDMA supports the SSP, I2S, UART, A/D Converter, and D/A Converter peripherals.
DMA can also be triggered by a timer match condition. Memory-to-memory transfers
and transfers to or from GPIO are also supported.
•
Scatter or gather DMA is supported through the use of linked lists. This means that
the source and destination areas do not have to occupy contiguous areas of memory.
•
Hardware DMA channel priority.
•
AHB slave DMA programming interface. The DMA Controller is programmed by
writing to the DMA control registers over the AHB slave interface.
•
One AHB bus master for transferring data. The interface transfers data when a DMA
request goes active.
•
32-bit AHB master bus width.
•
Incrementing or non-incrementing addressing for source and destination.
UM10360
Chapter 31: LPC17xx General Purpose DMA (GPDMA)
controller
Rev. 00.06 — 5 June 2009 User manual