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UM10360_0
© NXP B.V. 2009. All rights reserved.
User manual
Rev. 00.06 — 5 June 2009
496 of 808
NXP Semiconductors
UM10360
Chapter 25: LPC17xx Motor Control PWM
5.
Configuring other modules for MCPWM use
Configure the following registers in other modules before using the Motor Control PWM:
1. Power: in the PCONP register (
), set bit PCMCPWM.
Remark:
On reset the MCPWM is disabled (PCMCPWM = 0).
2. Peripheral clock: in the PCLKSEL1 register (
) select PCLK_MCPWM.
3. Pins: select MCPWM functions through the PINSEL registers. Select modes for these
pins through the PINMODE registers (
).
4. Interrupts: See
for motor control PWM related interrupts. Interrupts
can be enabled in the NVIC using the appropriate Interrupt Set Enable register.
6.
General Operation
includes detailed descriptions of the various modes of MCPWM operation,
but a quick preview here will provide background for the register descriptions below.
The MCPWM includes 3 channels, each of which controls a pair of outputs that in turn can
control something off-chip, like one set of coils in a motor. Each channel includes a
Timer/Counter (TC) register that is incremented by a processor clock (timer mode) or by
an input pin (counter mode).
Each channel has a Limit register that is compared to the TC value, and when a match
occurs the TC is “recycled” in one of two ways. In “edge-aligned mode” the TC is reset to
0, while in “centered mode” a match switches the TC into a state in which it decrements on
each processor clock or input pin transition until it reaches 0, at which time it starts
counting up again.
Each channel also includes a Match register that holds a smaller value than the Limit
register. In edge-aligned mode the channel’s outputs are switched whenever the TC
matches either the Match or Limit register, while in center-aligned mode they are switched
only when it matches the Match register.
So the Limit register controls the period of the outputs, while the Match register controls
how much of each period the outputs spend in each state. Having a small value in the
Limit register minimizes “ripple” if the output is integrated into a voltage, and allows the
MCPWM to control devices that operate at high speed.
The “downside” of small values in the Limit register is that they reduce the resolution of
the duty cycle controlled by the Match register. If you have 8 in the Limit register, the
Match register can only select the duty cycle among 0%, 12.5%, 25%, …, 87.5%, or
100%. In general, the resolution of each step in the Match value is 1 divided by the Limit
value.
This trade-off between resolution and period/frequency is inherent in the design of pulse
width modulators.