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UM10360_0
© NXP B.V. 2009. All rights reserved.
User manual
Rev. 00.06 — 5 June 2009
257 of 808
NXP Semiconductors
UM10360
Chapter 13: LPC17xx USB OTG controller
8.14 I
2
C Clock High Register (I2C_CLKHI - 0x5000 C30C)
The CLK register holds a terminal count for counting 48 MHz clock cycles to create the
high period of the slower I
2
C serial clock, SCL.
8.15 I
2
C Clock Low Register (I2C_CLKLO - 0x5000 C310)
The CLK register holds a terminal count for counting 48 MHz clock cycles to create the
low period of the slower I
2
C serial clock, SCL.
8.16 Interrupt handling
The interrupts set in the OTGIntSt register are set and cleared during HNP switching. All
OTG related interrupts, if enabled, are routed to the USB_OTG_INT bit in the USBIntSt
register.
6
RFDAIE
Receive Data Available Interrupt Enable. This enables the DAI interrupt to indicate that
data is available in the receive FIFO (i.e. not empty).
0
0
Disable the DAI.
1
Enable the DAI.
7
TFFIE
Transmit FIFO Not Full Interrupt Enable. This enables the Transmit FIFO Not Full interrupt
to indicate that the more data can be written to the transmit FIFO. Note that this is not full.
It is intended help the CPU to write to the I
2
C block only when there is room in the FIFO
and do this without polling the status register.
0
0
Disable the TFFI.
1
Enable the TFFI.
8
SRST
Soft reset. This is only needed in unusual circumstances. If a device issues a start
condition without issuing a stop condition. A system timer may be used to reset the I
2
C if
the bus remains busy longer than the time-out period. On a soft reset, the Tx and Rx
FIFOs are flushed, I2C_STS register is cleared, and all internal state machines are reset
to appear idle. The I2C_CLKHI, I2C_CLKLO and I2C_CTL (except Soft Reset Bit) are
NOT modified by a soft reset.
0
0
See the text.
1
Reset the I
2
C to idle state. Self clearing.
31:9 -
NA
Reserved, user software should not write ones to reserved bits. The value read from a
reserved bit is not defined.
NA
Table 244. I
2
C Control register (I2C_CTL - address 0x5000 C308) bit description
Bit
Symbol
Value
Description
Reset
Value
Table 245. I
2
C_CLKHI register (I2C_CLKHI - address 0x5000 C30C) bit description
Bit
Symbol
Description
Reset
Value
7:0
CDHI
Clock divisor high. This value is the number of 48 MHz
clocks the serial clock (SCL) will be high.
0xB9
Table 246. I
2
C_CLKLO register (I2C_CLKLO - address 0x5000 C310) bit description
Bit
Symbol
Description
Reset
Value
7:0
CDLO
Clock divisor low. This value is the number of 48 MHz
clocks the serial clock (SCL) will be low.
0xB9