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UM10360_0
© NXP B.V. 2009. All rights reserved.
User manual
Rev. 00.06 — 5 June 2009
25 of 808
1.
Summary of clocking and power control functions
This section describes the generation of the various clocks needed by the LPC17xx and
options of clock source selection, as well as power control and wake-up from reduced
power modes. Functions described in the following subsections include:
•
Oscillators
•
Clock source selection
•
PLLs
•
Clock dividers
•
APB dividers
•
Power control
•
Wake-up timer
•
External clock output
2.
Register description
All registers, regardless of size, are on word address boundaries. Details of the registers
appear in the description of each function.
UM10360
Chapter 4: LPC17xx Clocking and power control
Rev. 00.06 — 5 June 2009
User manual
Fig 6.
Clock generation for the LPC17xx
`
USB
Clock
Divider
osc_clk
irc_osc
system clock select
CLKSRCSEL[1:0]
USB PLL settings
(PLL1...)
USB clock divider setting
USBCLKCFG[3:0]
watchdog
pclk
Peripheral
Clock
Divider
wd_clk
usb_clk
pclk1
pclk8
pclk4
pclk2
USB PLL
(PL160M)
main PLL
settings
(PLL0...)
USB PLL
select
(PLL1CON)
Main PLL
(PL550M)
CPU
Clock
Divider
pllclk
CPU PLL
select
(PLL0CON)
cclk
watchdog clock select
WDCLKSEL[1:0]
rtc_clk
CPU clock divider setting
CCLKCFG[7:0]
sysclk