UM10462
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User manual
Rev. 5.5 — 21 December 2016
64 of 523
NXP Semiconductors
UM10462
Chapter 5: LPC11U3x/2x/1x Power profiles
5.6.1.4.4
System clock less than or equal to the expected value
command[0] = 12000;
command[1] = 25000;
command[2] = CPU_FREQ_LTE;
command[3] = 0;
(*rom)->pWRD->set_pll(command, result);
The above code specifies a 12 MHz PLL input clock, a system clock of no more than
25 MHz and no locking time-out.
set_pll
returns PLL_CMD_SUCCESS in
result[0]
and
24000 in
result[1]
. The new system clock is 24 MHz.
5.6.1.4.5
System clock greater than or equal to the expected value
command[0] = 12000;
command[1] = 25000;
command[2] = CPU_FREQ_GTE;
command[3] = 0;
(*rom)->pWRD->set_pll(command, result);
The above code specifies a 12 MHz PLL input clock, a system clock of at least 25 MHz
and no locking time-out.
set_pll
returns PLL_CMD_SUCCESS in
result[0]
and 36000 in
result[1]
. The new system clock is 36 MHz.
5.6.1.4.6
System clock approximately equal to the expected value
command[0] = 12000;
command[1] = 16500;
command[2] = CPU_FREQ_APPROX;
command[3] = 0;
(*rom)->pWRD->set_pll(command, result);
The above code specifies a 12 MHz PLL input clock, a system clock of approximately
16.5 MHz and no locking time-out.
set_pll
returns PLL_CMD_SUCCESS in
result[0]
and
16000 in
result[1]
. The new system clock is 16 MHz.
5.7 Power routine
5.7.1 set_power
This routine configures the device’s internal power control settings according to the calling
arguments. The goal is to reduce active power consumption while maintaining the feature
of interest to the application close to its optimum.
Remark:
The set_power routine was designed for systems employing the configuration of
SYSAHBCLKDIV = 1 (System clock divider register, see
). Using
this routine in an application with the system clock divider not equal to 1 might not improve
microcontroller’s performance as much as in setups when the main clock and the system
clock are running at the same rate.
set_power
returns a result code that reports whether the power setting was successfully
changed or not.
