UM10462
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© NXP B.V. 2016. All rights reserved.
User manual
Rev. 5.5 — 21 December 2016
63 of 523
NXP Semiconductors
UM10462
Chapter 5: LPC11U3x/2x/1x Power profiles
Remark:
The time it takes the PLL to lock depends on the selected PLL input clock
source (IRC/system oscillator) and its characteristics. The selected source can
experience more or less jitter depending on the operating conditions such as power
supply and/or ambient temperature. This is why it is suggested that when a good known
clock source is used and a PLL_NOT_LOCKED response is received, the set_pll routine
should be invoked several times before declaring the selected PLL clock source invalid.
Hint:
setting
Param3
equal to the system PLL frequency [Hz] divided by 10000 will
provide more than enough PLL lock-polling cycles.
5.6.1.4 Code examples
The following examples illustrate some of the features of
set_pll
discussed above.
5.6.1.4.1
Invalid frequency (device maximum clock rate exceeded)
command[0] = 12000;
command[1] = 60000;
command[2] = CPU_FREQ_EQU;
command[3] = 0;
(*rom)->pWRD->set_pll(command, result);
The above code specifies a 12 MHz PLL input clock and a system clock of exactly
60 MHz. The application was ready to infinitely wait for the PLL to lock. But the expected
system clock of 60 MHz exceeds the maximum of 50 MHz. Therefore
set_pll
returns
PLL_INVALID_FREQ in
result[0]
and 12000 in
result[1]
without changing the PLL
settings.
5.6.1.4.2
Invalid frequency selection (system clock divider restrictions)
command[0] = 12000;
command[1] = 40;
command[2] = CPU_FREQ_LTE;
command[3] = 0;
(*rom)->pWRD->set_pll(command, result);
The above code specifies a 12 MHz PLL input clock, a system clock of no more than
40 kHz and no time-out while waiting for the PLL to lock. Since the maximum divider value
for the system clock is 255 and running at 40 kHz would need a divide by value of 300,
set_pll
returns PLL_INVALID_FREQ in
result[0]
and 12000 in
result[1]
without changing
the PLL settings.
5.6.1.4.3
Exact solution cannot be found (PLL)
command[0] = 12000;
command[1] = 25000;
command[2] = CPU_FREQ_EQU;
command[3] = 0;
(*rom)->pWRD->set_pll(command, result);
The above code specifies a 12 MHz PLL input clock and a system clock of exactly
25 MHz. The application was ready to infinitely wait for the PLL to lock. Since there is no
valid PLL setup within earlier mentioned restrictions,
set_pll
returns
PLL_FREQ_NOT_FOUND in
result[0]
and 12000 in
result[1]
without changing the PLL
settings.
