UM10429
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2010. All rights reserved.
User manual
Rev. 1 — 20 October 2010
101 of 258
NXP Semiconductors
UM10429
Chapter 11: LPC1102 SPI0 with SSP
In this configuration, during idle periods:
•
The CLK signal is forced HIGH.
•
SSEL is forced HIGH.
•
The transmit MOSI/MISO pad is in high impedance.
If the SPI/SSP is enabled and there is valid data within the transmit FIFO, the start of
transmission is signified by the SSEL master signal being driven LOW, which causes
slave data to be immediately transferred onto the MISO line of the master. Master’s MOSI
pin is enabled.
One half period later, valid master data is transferred to the MOSI line. Now that both the
master and slave data have been set, the SCK master clock pin becomes LOW after one
further half SCK period. This means that data is captured on the falling edges and be
propagated on the rising edges of the SCK signal.
In the case of a single word transmission, after all bits of the data word are transferred, the
SSEL line is returned to its idle HIGH state one SCK period after the last bit has been
captured.
However, in the case of continuous back-to-back transmissions, the SSEL signal must be
pulsed HIGH between each data word transfer. This is because the slave select pin
freezes the data in its serial peripheral register and does not allow it to be altered if the
CPHA bit is logic zero. Therefore the master device must raise the SSEL pin of the slave
device between each data transfer to enable the serial peripheral data write. On
completion of the continuous transfer, the SSEL pin is returned to its idle state one SCK
period after the last bit has been captured.
a. Single transfer with CPOL=1 and CPHA=0
b. Continuous transfer with CPOL=1 and CPHA=0
Fig 16. SPI frame format with CPOL = 1 and CPHA = 0 (a) Single and b) Continuous Transfer)
SCK
SSEL
Q
MSB
LSB
4 to 16 bits
MISO
MOSI
MSB
LSB
SCK
SSEL
MOSI
MISO
4 to 16 bits
4 to 16 bits
MSB
LSB
MSB
LSB
Q
MSB
LSB
Q
MSB
LSB
