UM10503
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User manual
Rev. 1.3 — 6 July 2012
821 of 1269
NXP Semiconductors
UM10503
Chapter 28: LPC43xx State Configurable Timer (SCT)
28.6.6 SCT start condition register
If UNIFY = 1 in the CONFIG register, only the _L bits are used.
If UNIFY = 0 in the CONFIG register, this register can be written to as two registers
START_L (address 0x4000 4014) and START_H (address 0x4000 4016). Both the L and
H registers can be read or written individually or in a single 32-bit read or write operation.
The bits in this register select which events, if any, clear the STOP bit in the Control
register. (Since no events can occur when HALT is 1, only software can clear the HALT bit
by writing the Control register.)
28.6.7 SCT counter register
If UNIFY = 1 in the CONFIG register, the counter is a unified 32-bit register and both the
_L and _H bits are used.
If UNIFY = 0 in the CONFIG register, this register can be written to as two registers
COUNT_L (address 0x4000 4040) and COUNT_H (address 0x4000 4042). Both the L
and H registers can be read or written individually or in a single 32-bit read or write
operation. In this case, the L and H registers count independently under the control of the
other registers.
Attempting to write a counter while it is running does not affect the counter but produces a
bus error. Software can read the counter registers at any time.
Table 651. SCT stop condition register (STOP - address 0x4000 0010) bit description
Bit
Symbol
Description
Reset
value
15:0
STOPMSK_L
If bit n is one, event n sets the STOP_L bit in the CTRL register
(event 0 = bit 0, event 1 = bit 1, event 15 = bit 15).
0
31:16 STOPMSK_H
If bit n is one, event n sets the STOP_H bit in the CTRL register
(event 0 = bit 16, event 1 = bit 17, event 15 = bit 31).
0
Table 652. SCT start condition register (START - address 0x4000 0014) bit description
Bit
Symbol
Description
Reset
value
15:0
STARTMSK_L
If bit n is one, event n clears the STOP_L bit in the CTRL
register (event 0 = bit 0, event 1 = bit 1, event 15 = bit 15).
0
31:16 STARTMSK_H
If bit n is one, event n clears the STOP_H bit in the CTRL
register (event 0 = bit 16, event 1 = bit 17, event 15 = bit 31).
0
Table 653. SCT counter register (COUNT - address 0x4000 0040) bit description
Bit
Symbol
Description
Reset
value
15:0
CTR_L
When UNIFY = 0, read or write the 16-bit L counter value. When
UNIFY = 1, read or write the lower 16 bits of the 32-bit unified
counter.
0
31:16
CTR_H
When UNIFY = 0, read or write the 16-bit H counter value. When
UNIFY = 1, read or write the upper 16 bits of the 32-bit unified
counter.
0
