NXP Semiconductors LCP43 Series, User Manual

Page: 820 / 1269

UM10503 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved.
User manual Rev. 1.3 — 6 July 2012 820 of 1269
NXP Semiconductors
UM10503
Chapter 28: LPC43xx State Configurable Timer (SCT)
If UNIFY = 0 in the CONFIG register, this register can be written to as two registers
LIMIT_L (address 0x4000 4008) and LIMIT_H (address 0x4000 400A). Both the L and H
registers can be read or written individually or in a single 32-bit read or write operation.
The bits in this register set which events act as counter limits. When a limit event occurs,
the counter is cleared to zero in unidirectional mode or begins counting down in
bidirectional mode. When the counter reaches all ones, this state is always treated as a
limit event, and the counter is cleared in unidirectional mode or, in bidirectional mode,
begins counting down on the next clock edge - even if no limit event as defined by the
SCT limit register has occurred.
28.6.4 SCT halt condition register
If UNIFY = 1 in the CONFIG register, only the _L bits are used.
If UNIFY = 0 in the CONFIG register, this register can be written to as two registers
HALT_L (address 0x4000 400C) and HALT_H (address 0x4000 400E). Both the L and H
registers can be read or written individually or in a single 32-bit read or write operation.
Remark: Any event halting the counter disables its operation until software clears the
HALT bit (or bits) in the CTRL register ( Table 648 ).
28.6.5 SCT stop condition register
If UNIFY = 1 in the CONFIG register, only the _L bits are used.
If UNIFY = 0 in the CONFIG register, this register can be written to as two registers
STOPT_L (address 0x4000 4010) and STOP_H (address 0x4000 4012). Both the L and H
registers can be read or written individually or in a single 32-bit read or write operation.
Table 649. SCT limit register (LIMIT - address 0x4000 0008) bit description
Bit Symbol Description Reset
value
15:0 LIMMSK_L If bit n is one, event n is used as a counter limit for the L or
unified counter (event 0 = bit 0, event 1 = bit 1, event 15 =
bit 15). 0
31:16 LIMMSK_H If bit n is one, event n is used as a counter limit for the H
counter (event 0 = bit 16, event 1 = bit 17, event 15 = bit
31). 0
Table 650. SCT halt condition register (HALT - address 0x4000 000C) bit description
Bit Symbol Description Reset
value
15:0 HALTMSK_L If bit n is one, event n sets the HALT_L bit in the CTRL register
(event 0 = bit 0, event 1 = bit 1, event 15 = bit 15). 0
31:16 HALTMSK_H If bit n is one, event n sets the HALT_H bit in the CTRL register
(event 0 = bit 16, event 1 = bit 17, event 15 = bit 31). 0