NXP Semiconductors Kinetis KE1xZ256, Reference Manual

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Chapter 6
Memory-Mapped Divide and Square Root (MMDVSQ)
6.1 Chip-specific Information for this Module
In this block chapter, PBRIDGE stands for the Peripheral Bridge, with the same meaning
as AIPS-Lite.
6.2 Introduction
ARM processor cores in the Cortex-M family implementing the ARMv6-M instruction
set architecture do not include hardware support for integer divide operations. The
affected processors include the Cortex-M0+ core. However, in certain deeply embedded
application spaces, hardware support for this class of arithmetic operation (along with an
unsigned square root function) is important to maximize system performance and
minimize device power dissipation. Accordingly, the MMDVSQ module is included in
select microcontrollers, to serve as a memory-mapped co-processor located in a special
address space (within the system memory map) that is accessible only to the processor
core.
The MMDVSQ module supports execution of the integer divide operations defined in the
ARMv7-M instruction set architecture, plus an unsigned integer square root operation.
The supported integer divide operations include 32/32 signed (SDIV) and unsigned
(UDIV) calculations.
6.2.1 Features
The key features of the MMDVSQ include:
• Lightweight implementation of 32-bit integer divide and square root arithmetic
operations
Kinetis KE1xZ256 Sub-Family Reference Manual, Rev. 3, 07/2018
NXP Semiconductors 79