NXP Semiconductors Kinetis KE1xZ256, Reference Manual

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• The Filter block acts as a simple sampler if the filter is bypassed and
C0[FILTER_CNT] is set to 0x01.
• The Filter block filters based on multiple samples when the filter is bypassed and
C0[FILTER_CNT] is set greater than 0x01.
• If C0[SE] = 1, the external SAMPLE input is used as the sampling clock.
• IF C0[SE] = 0, the divided bus clock is used as the sampling clock.
• If enabled, the Filter block will incur up to one bus clock additional latency penalty
on COUT due to the fact that COUT, which crosses clock domain boundaries, must
be resynchronized to the bus clock.
• C0[WE] and C0[SE] are mutually exclusive.
• If enabled, the filter clock and the sample period must be at least 4 times slower than
the system clock to the comparator.
37.6 CMP pin descriptions
This section provides the comparator pin descriptions. The external inputs IN[7:0] are
muxed by CMP_C1[PSEL] and CMP_C1[MSEL] beforehand and multiplexed output
will then go to the second stage of multiplex with the input of 8-bit DAC and other two
internal reserved test signals, determined by CMP_C1[INPSEL] and CMP_C1[INNSEL].
The output of the second multiplex will finally go to the positive and negative ports of the
comparator respectively.
Table 37-2. CMP signal descriptions
Signal Description I/O
IN[7:0] Analog voltage inputs I
NOTE
If comparing one input channel with the DAC output, and if
there is injection or over-voltage in the input channels, the DAC
output may be corrupted. For such case, the software
workaround is to configure the DAC side SEL[2:0] same as the
non-DAC side, i.e. configuration of MSEL and PSEL register
bits must be the same.
CMP pin descriptions
Kinetis KE1xZ256 Sub-Family Reference Manual, Rev. 3, 07/2018
788 NXP Semiconductors