NXP Semiconductors Kinetis KE1xZ256, Reference Manual

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• Interrupt request to CPU with interrupt vector for an interrupt service routine
(ISR)
• Forced reset occurs 128 bus clocks after the interrupt vector fetch.
• Configuration bits are write-once-after-reset to ensure watchdog configuration cannot
be mistakenly altered.
• Robust write sequence for unlocking write-once configuration bits
• Unlock sequence of writing 0xC520 and then 0xD928 for allowing updates to
write-once configuration bits
• Software must make updates within 128 bus clocks after unlocking and before
WDOG closing unlock window.
29.2.2 Block diagram
The following figure shows a block diagram of the WDOG module.
MUX
MUX
MUX
ERCLK
SIRC
UPDATE EN
CLK PRES WIN INT
BUS_CLK
256
16-bit Window Register
0xD928
0xC520 Control Status 128 Bus Cycle
Disable Protect
Bit Write Control
Protect
Window
Reset
Counter
Overflow
Counter
Write Control
0xA602
0xB480
16-bit Timeout Value Register
Refresh Sequence
Compare Logic
16-bit Counter Register
Compare Logic
Control
Logic
128 Bus
CPU Reset
IRQ Interrupt
Clock Delay
Backup Reset
(8 MHz IRC
LPO_CLK
from SCG)
(external ref clock
from SCG)
Figure 29-1. WDOG block diagram
29.3 Memory map and register definition
Chapter 29 Watchdog timer (WDOG)
Kinetis KE1xZ256 Sub-Family Reference Manual, Rev. 3, 07/2018
NXP Semiconductors 607