NXP Semiconductors Kinetis KE1xZ256, Reference Manual

Page: 603 / 1325

Table 28-3. EWM low-power modes
Module mode Chip mode
Wait Wait, VLPW
Stop Stop, VLPS
28.5.2 EWM_out pin state in low power modes
During Wait, Stop, and Power Down modes the EWM_out pin preserve its state before
entering Wait or Stop mode. When the CPU enters a Run mode from Wait or Stop
recovery, the pin resumes its previous state before entering Wait or Stop mode. When the
CPU enters Run mode from Power Down, the pin returns to its reset state.
28.5.3 Example code
28.5.3.1 Initializing the EWM
The following code segment shows the initialize sequence of the EWM module. It
enables EWM_in pin input with assert state logic zero, enables interrupt when EWM_out
is assert. The compare value is also set into CMPL/H register before enabling EWM.
// Initialize the EWM module
EWM_CMPL = compareValue & 0xFF;
EWM_CMPH = (compareValue >> 8) 0xFF;
EWM_CTRL = EWM_CTRL_INEN(1) | EWM_CTRL_ASSIN(0) |
EWM_CTRL_INTEN(1) | EWM_CTRL_EWMEN(1);
28.5.3.2 Refreshing the EWM
The following code segment shows the refresh write sequence of the EWM module.
// Refresh EWM
DisableInterrupts; // disable global interrupt
EWM_SERV= 0xB4; // write the 1st refresh words
EWM_SERV= 0x2C; // write the 2nd refresh words
EnableInterrupts; // enable global interrupt
Chapter 28 External Watchdog Monitor (EWM)
Kinetis KE1xZ256 Sub-Family Reference Manual, Rev. 3, 07/2018
NXP Semiconductors 603