NXP Semiconductors Kinetis KE1xZ256, Reference Manual

Page: 461 / 1325

• Reads the start program counter (PC) from vector-table offset 4
• Link register (LR) is set to 0xFFFF_FFFF
The on-chip peripheral modules are disabled and the non-analog I/O pins are initially
configured as disabled. The pins with analog functions assigned to them are assigned by
default to their analog functions after reset.
During and following a reset, the SWD pins have their associated input pins configured
as:
• SWD_CLK in pull-down (PD)
• SWD_DIO in pull-up (PU)
21.2.2.1 External pin reset (PIN)
On this device, asserting RESET wakes and resets the device from any mode. During a
pin reset, RCM_SRS[PIN] is set.
The RESET pin filter supports filtering from both the 1 kHz LPO clock and the bus
clock. RCM_RPC[RSTFLTSS], RCM_RPC[RSTFLTSRW], and
RCM_RPC[RSTFLTSEL] control this functionality; see the
RCM chapter. The filters are
asynchronously reset by Chip POR. The reset value for each filter assumes the RESET
pin is negated.
For all stop modes where LPO clock is still active, the only filtering option is the LPO-
based digital filter. The filtering logic either switches to bypass operation or has
continued filtering operation depending on the filtering mode selected.
The LPO filter has a fixed filter value of 3. Due to a synchronizer on the input data, there
is also some associated latency (2 cycles). As a result, 5 cycles are required to complete a
transition from low to high or high to low.
21.2.2.2 Low voltage detect (LVD)
The chip includes a system for managing low voltage conditions to protect memory
contents and control MCU system states during supply voltage variations. The system
consists of a power-on reset (POR) circuit and an LVD circuit. The LVD system can
always be enabled in normal Run, or Wait mode. The LVD system is disabled (LVR
active only) when entering VLPx modes or Stop mode.
Chapter 21 Reset and Boot
Kinetis KE1xZ256 Sub-Family Reference Manual, Rev. 3, 07/2018
NXP Semiconductors 461