NXP Semiconductors Kinetis KE1xZ256, Reference Manual

Page: 412 / 1325

• Clock gating
• Clock source selection
• Clock divide values
The following figure is a block diagram of the PCC clock source selection and clock
gating. Some peripherals also have a clock divider available. See the peripheral's PCC
register for more information.
PCC - Peripheral Clock Muxing and Gating
Peripheral clock select
(PCS bits in
the Peripheral's
PCC register).
Peripheral Functional Clock
Clock
Divider
Clock Divider
only available for
certain peripherals
Clock Sources
from Clock Generator
Module
External
Peripheral-Specific
Clock Source
This clock is used by the Peripheral
Functional Logic
(example - derive baud rates)
Clock Divide
Control
(PCD bits in
the Peripheral's
PCC register).
Post-Divider Mux
Control
(Ext Clk selected
if PCS=000)
Clock Gate
Control
Clock
Gate
PCC Register values
& Test Control Signals
Peripheral Interface Clock
This clock is used by PCC
Control and Config Registers
Bus Clock
Figure 20-1. PCC Clock Source Selection and Gating
20.3 Functional description
The Peripheral Clock Control (PCC) module provides clock gating and clock source
selection to each peripheral.
Functional description
Kinetis KE1xZ256 Sub-Family Reference Manual, Rev. 3, 07/2018
412 NXP Semiconductors