NXP Semiconductors Kinetis KE1xZ256, Reference Manual

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15.1.4 Memory map and register descriptions
The MCM's programming model provides control and configuration of the FAU's
features. For details, see the description of the MCM's Platform Control Register
(PLACR).
15.1.5 Functional description
The FAU is a flash acceleration unit with flexible buffers for user configuration.
Besides managing the interface between bus masters and the program flash memory and
FlexMemory, the FAU can be used to customize the program flash memory cache and
buffer to provide single-cycle system clock data access times. Whenever a hit occurs for
the prefetch speculation buffer or the cache (when enabled), the requested data is
transferred within a single system clock.
Upon system reset, the FAU is configured as follows:
• Flash cache is enabled.
• Instruction speculation and caching are enabled.
• Data speculation is disabled.
• Data caching is enabled.
Though the default configuration provides flash acceleration, advanced users may desire
to customize the FAU buffer configurations to maximize throughput for their use cases.
For example, the user may adjust the controls to enable buffering per access type (data or
instruction).
NOTE
When reconfiguring the FAU, do not program the control and
configuration inputs to the FAU while the program flash
memory or FlexMemory is being accessed. Instead, change
them with a routine executing from RAM in supervisor mode.
15.2 Usage Guide
For many systems the on-chip flash is the main memory. The Flash Acceleration Unit
(FAU) is the interface between the flash memory blocks and the system. In a typical
configuration, the core and system bus clock speeds are clock significantly faster than the
flash memory clock. The FAU includes features designed to accelerate flash accesses.
Usage Guide
Kinetis KE1xZ256 Sub-Family Reference Manual, Rev. 3, 07/2018
280 NXP Semiconductors