NXP Semiconductors Kinetis KE1xZ256, Reference Manual

Page: 253 / 1325

The following figure lists the memory array terms and how the TCD settings interrelate.
xADDR: (Starting address)
xLAST: Number of bytes added to
current address after major loop
(typically used to loop back)
Minor loop
(NBYTES in
minor loop,
often the same
value as xSIZE)
Minor loop
Last minor loop
Offset (xOFF): number of bytes added to
current address after each transfer
(often the same value as xSIZE)
Each DMA source (S) and
destination (D) has its own:
Address (xADDR)
Size (xSIZE)
Offset (xOFF)
Modulo (xMOD)
Last Address Adjustment (xLAST)
where x = S or D
Peripheral queues typically
have size and offset equal
to NBYTES.
xSIZE: (size of one
data transfer)
Figure 13-6. Memory array terms
13.5.2 Programming errors
The eDMA performs various tests on the transfer control descriptor to verify consistency
in the descriptor data. Most programming errors are reported on a per channel basis with
the exception of channel priority error (ES[CPE]).
For all error types other than channel priority error, the channel number causing the error
is recorded in the Error Status register (DMAx_ES). If the error source is not removed
before the next activation of the problem channel, the error is detected and recorded
again.
If priority levels are not unique, when any channel requests service, a channel priority
error is reported. The highest channel priority with an active request is selected, but the
lowest numbered channel with that priority is selected by arbitration and executed by the
eDMA engine. The hardware service request handshake signals, error interrupts, and
error reporting is associated with the selected channel.
13.5.3 Arbitration mode considerations
This section discusses arbitration considerations for the eDMA.
Chapter 13 Enhanced Direct Memory Access (eDMA)
Kinetis KE1xZ256 Sub-Family Reference Manual, Rev. 3, 07/2018
NXP Semiconductors 253