NXP Semiconductors Kinetis KE1xZ256, Reference Manual

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Field Function
When this field is set, the built in FIFO structure for the receive buffer is enabled. The size of the FIFO
structure is indicated by the RXFIFOSIZE field. If this field is not set, the receive buffer operates as a
FIFO of depth one dataword regardless of the value in RXFIFOSIZE. Both CTRL[TE] and CTRL[RE] must
be cleared prior to changing this field.
0 - Receive FIFO is not enabled. Buffer is depth 1. (Legacy support)
1 - Receive FIFO is enabled. Buffer is depth indicted by RXFIFOSIZE.
2-0
RXFIFOSIZE
Receive FIFO. Buffer Depth
The maximum number of receive datawords that can be stored in the receive buffer before an overrun
occurs. This field is read only.
000 - Receive FIFO/Buffer depth = 1 dataword.
001 - Receive FIFO/Buffer depth = 4 datawords.
010 - Receive FIFO/Buffer depth = 8 datawords.
011 - Receive FIFO/Buffer depth = 16 datawords.
100 - Receive FIFO/Buffer depth = 32 datawords.
101 - Receive FIFO/Buffer depth = 64 datawords.
110 - Receive FIFO/Buffer depth = 128 datawords.
111 - Receive FIFO/Buffer depth = 256 datawords.
46.3.1.13 LPUART Watermark (WATER)
46.3.1.13.1 Address
Register Offset
WATER Base a 2Ch offset
46.3.1.13.2 Function
This register provides the ability to set a programmable threshold for notification of
needing additional transmit data. This register may be read at any time but must be
written only when CTRL[TE] is not set.
46.3.1.13.3 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R RXCOUNT
RXWATER
W
Reset
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R TXCOUNT
TXWATER
W
Reset
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Register definition
Kinetis KE1xZ256 Sub-Family Reference Manual, Rev. 3, 07/2018
1204 NXP Semiconductors