NXP Semiconductors Kinetis KE1xZ256, Reference Manual

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0
1 2 3 4 5
counter read result: 5 pwtclk
counter read result: 5 pwtclk
BUSCLK
PWTCLK
PWTCNT
PWTIN
actual pulse width: 5 err actual pulse width: 5 err
0
0
1 2 3 4
5
(err < 1 1 bus clock)
Figure 41-10. Example at PWTCLK is bus clock divided by 4
0
1 2
counter read result: 2 pwtclk
counter read result: 2 pwtclk
BUSCLK
PWTCLK
PWTCNT
PWTIN
actual pulse width: 2 err
actual pulse width: 2 err
0
(err < 1 1 bus clock)
0
1 2
Figure 41-11. Example at PWTCLK is bus clock divided by 8
41.8 Initialization/Application information
Following are the recommended steps to initialize the PWT module:
1. Configure PWTxCR to select clock source, set pre-scaler rate, select PWT input pin
and edge detection mode.
2. Set PWTIE, PRDYIE and POVIE bits in PWTxCS if corresponding interrupt is
desired to be generated.
3. Set PWTEN bit in PWTxCS to enable the pulse width measurement.
Chapter 41 Pulse Width Timer (PWT)
Kinetis KE1xZ256 Sub-Family Reference Manual, Rev. 3, 07/2018
NXP Semiconductors 1049