NXP Semiconductors KE1xF Series, Reference Manual, Page: 963 / 1483

• Direct access to input pin states
• Dual edge capture for pulse and period width measurement
• Quadrature decoder with prescaled input filters, relative position counting, and
interrupt on position count or capture of position count on external event
• The FTM channels can be selected to generate a trigger pulse on channel output
instead of a PWM
• Dithering capability to simulate fine edge control for both PWM period or PWM
duty cycle
41.2.3 Modes of operation
When the chip is in an active Debug mode, the FTM temporarily suspends all counting
until the chip returns to normal user operating mode. During Stop mode, all FTM input
clocks are stopped, so the FTM is effectively disabled until clocks resume. During Wait
mode, the FTM continues to operate normally. If the FTM does not need to produce a
real time reference or provide the interrupt sources needed to wake the chip from Wait
mode, the power can then be saved by disabling FTM functions before entering Wait
mode.
41.2.4 Block Diagram
The FTM uses one input/output (I/O) pin per channel, CHn (FTM channel (n)) where n is
the channel number (0–7).
NOTE
The number of channels supported can vary for each instance of
the FTM module on a chip. See the chip-specific FTM
information to see how many channels are supported for each
module instance. For example, if a module instance supports
only six channels, references to channel numbers 6 and 7 do not
apply for that instance.
The following figure shows the FTM structure. The central component of the FTM is the
16-bit counter with programmable initial and final values and its counting can be up or
up-down.
Chapter 41 FlexTimer Module (FTM)
Kinetis KE1xF Sub-Family Reference Manual, Rev. 4, 06/2019
NXP Semiconductors 963