NXP Semiconductors KE1xF Series, Reference Manual, Page: 953 / 1483

PDB counter
Ch n pre-trigger 0
Ch n pre-trigger 1
CH n DLY1
CH n DLY0
SC[LDOK]
Figure 40-10. Registers update with SC[LDMOD] = x1
40.5.6 Interrupts
PDB can generate two interrupts: PDB interrupt and PDB sequence error interrupt. The
following table summarizes the interrupts.
Table 40-4. PDB interrupt summary
Interrupt Flags Enable bit
PDB Interrupt SC[PDBIF] SC[PDBIE] = 1 and
SC[DMAEN] = 0
PDB Sequence Error Interrupt CH n S[ERR m ] SC[PDBEIE] = 1
40.5.7 DMA
If SC[DMAEN] is set, PDB can generate a DMA transfer request when SC[PDBIF] is
set. When DMA is enabled, the PDB interrupt is not issued.
40.6 Application information
Chapter 40 Programmable Delay Block (PDB)
Kinetis KE1xF Sub-Family Reference Manual, Rev. 4, 06/2019
NXP Semiconductors 953