NXP Semiconductors KE1xF Series, Reference Manual, Page: 947 / 1483

PDBx_POnDLY field descriptions (continued)
Field Description
40.5 Functional description
40.5.1 PDB pre-trigger and trigger outputs
The PDB contains a counter whose output is compared to several different digital values.
If the PDB is enabled, then a trigger input event will reset the counter and make it start to
count. A trigger input event is defined as a rising edge being detected on a selected
trigger input source, or if a software trigger is selected and the Software Trigger bit
(SC[SWTRIG]) is written with 1. For each channel, a delay m determines the time
between assertion of the trigger input event to the time at which changes in the pre-
trigger m output signal are started. The time is defined as:
• Trigger input event to pre-trigger m = (prescaler × multiplication factor × delay m) +
2 peripheral clock cycles
• Add 1 additional peripheral clock cycle to determine the time when the channel
trigger output changes.
Each channel is associated with 1 ADC block. PDB channel n pre-trigger outputs 0 to M;
each pre-trigger output is connected to ADC hardware trigger select and hardware trigger
inputs. The pre-triggers are used to precondition the ADC block before the actual trigger
occurs. When the ADC receives the rising edge of the trigger, the ADC will start the
conversion according to the precondition determined by the pre-triggers. The ADC
contains M sets of configuration and result registers, allowing it to alternate conversions
between M different analog sources (like a ping-pong game). The pre-trigger outputs are
used to specify which signal will be sampled next. When a pre-trigger m is asserted, the
ADC conversion is triggered with set m of the configuration and result registers.
The waveforms shown in the following diagram show the pre-trigger and trigger outputs
of PDB channel n. The delays can be independently set using the channel delay registers
(CHnDLYm), and the pre-triggers can be enabled or disabled using the PDB Channel
Pre-Trigger Enables (CHnC1[EN[m]]).
Chapter 40 Programmable Delay Block (PDB)
Kinetis KE1xF Sub-Family Reference Manual, Rev. 4, 06/2019
NXP Semiconductors 947