NXP Semiconductors KE1xF Series, Reference Manual, Page: 922 / 1483

40.1.2 PDB Clock Options
The PDB module is clocked by the system clock (SYS_CLK). The SYS_CLK could run
up to CPU frequency which provides higher timing resolution and more precise delay
control with the PDB counter.
40.1.3 PDB Module Interconnections
Besides the specific PDB to ADC triggering scheme (refer to the
"ADC trigger source" section), the PDB channel triggers can also work as trigger source
of TRGMUX module, which can be used to trigger other modules besides ADC.
Following are PDB module inter-connectivities:
PDBx Trigger outputs Interconnectivity
ADC Channel 0 triggers ADC trigger connects to both ADC and TRGMUX
DAC triggers DAC trigger connects to TRGMUX
Pulse-out Pulse-out connects to TRGMUX
40.1.3.1 Back-to-back acknowledgement connections
Back-to-back operation enables the ADC conversions complete to trigger the next PDB
channel pre-trigger and trigger output.
In this MCU, the following PDB back-to-back operation acknowledgment connections
are implemented based on SIM_CHIPCTL[PDB_BB_SEL] bit setting.
When SIM_CHIPCTL[PDB_BB_SEL]=0:
The PDB back-to-back operation acknowledgement connections are implemented inside
each PDB unit as a ring. The following list is an example for PDB0.
• PDB0 channel 0 pre-trigger 0 acknowledgement input: ADC0SC1H_COCO
• PDB0 channel 0 pre-trigger 1 acknowledgement input: ADC0SC1A_COCO
• PDB0 channel 0 pre-trigger 2 acknowledgement input: ADC0SC1B_COCO
• PDB0 channel 0 pre-trigger 3 acknowledgement input: ADC0SC1C_COCO
• PDB0 channel 0 pre-trigger 4 acknowledgement input: ADC0SC1D_COCO
• PDB0 channel 0 pre-trigger 5 acknowledgement input: ADC0SC1E_COCO
• PDB0 channel 0 pre-trigger 6 acknowledgement input: ADC0SC1F_COCO
• PDB0 channel 0 pre-trigger 7 acknowledgement input: ADC0SC1G_COCO
The back-to-back chain diagram is as follows:
Chip-specific information for this module
Kinetis KE1xF Sub-Family Reference Manual, Rev. 4, 06/2019
922 NXP Semiconductors