NXP Semiconductors KE1xF Series, Reference Manual, Page: 708 / 1483

Table 30-1. WDOG low-power modes
Module mode Chip mode
Wait Wait, VLPW
Stop Stop, VLPS
30.2 Introduction
The Watchdog Timer (WDOG) module is an independent timer that is available for
system use. It provides a safety feature to ensure that software is executing as planned
and that the CPU is not stuck in an infinite loop or executing unintended code. If the
WDOG module is not serviced (refreshed) within a certain period, it resets the MCU.
30.2.1 Features
Features of the WDOG module include:
• Configurable clock source inputs independent from the bus clock
• Bus clock (slow clock)
• LPO clock (from PMC)
• SIRC (8 MHz IRC from SCG)
• ERCLK (external reference clock from SCG)
• Programmable timeout period
• Programmable 16-bit timeout value
• Optional fixed 256 clock prescaler when longer timeout periods are needed
• Robust write sequence for counter refresh
• Refresh sequence of writing 0xA602 and then 0xB480
• Window mode option for the refresh mechanism
• Programmable 16-bit window value
• Provides robust check that program flow is faster than expected
• Early refresh attempts trigger a reset.
• Optional timeout interrupt to allow post-processing diagnostics
Introduction
Kinetis KE1xF Sub-Family Reference Manual, Rev. 4, 06/2019
708 NXP Semiconductors