NXP Semiconductors KE1xF Series, Reference Manual, Page: 353 / 1483

15.3.12 On-Chip Memory Descriptor Register (MSCM_OCMDRn)
This section of the programming model is an array of 32-bit generic on-chip memory
descriptor registers that provide static information on the attached memories as well as
configurable controls (where appropriate).
Privileged 32-bit reads from a processor core or the debugger return the appropriate
processor information. Reads from any other bus master return all zeroes. Privileged
writes from a processor core or the debugger to writeable registers update the appropriate
fields. Privileged writes from other bus masters are ignored. Attempted user mode
accesses or any access with a size other than 32 bits are terminated with an error.
Address: 4000_1000h base + 400h (4d × i), where i=0d to 3d
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
V
Reserved
Reserved
OCMSZH
OCMSZ
Reserved
OCMW RO
W
Reset x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x*
Chapter 15 Miscellaneous System Control Module (MSCM)
Kinetis KE1xF Sub-Family Reference Manual, Rev. 4, 06/2019
NXP Semiconductors 353