NXP Semiconductors KE1xF Series, Reference Manual, Page: 334 / 1483

The Local Memory Controller address decode logic routes these accesses and also
provides any crossbar switch slave target logic. Finally, the Local Memory controller
provides the needed MPU connections for checking all SRAM controller and cacheable
accesses.
The programming model for the Code Cache is accessed via the core's Private Peripheral
Bus (PPB).
14.4.1.1 Processor Code accesses
Processor Code accesses are routed to the SRAM_L if they are mapped to that space. All
other PC accesses are routed to the Code Cache Memory Controller. This controller then
processes the cacheable accesses as needed, while bypassing the non-cacheable, cache
write-through, cache miss, and cache maintenance accesses to the CCM bus and the
crossbar switch using the Master0 port.
14.4.1.2 Processor System accesses
Processor System accesses are routed to the SRAM_U if they are mapped to that space.
All other PS accesses are routed to the CCM bus and the crossbar switch using the
Master1 port.
14.4.1.3 Backdoor port accesses
All LMEM backdoor port accesses are for the SRAM controller. These accesses go to the
SRAM_L or the SRAM_U depending on their specific address.
14.4.2 SRAM Function
14.4.2.1 SRAM Configuration
The figure below shows how the SRAM controller is configured. See chip-specific
memory information for on-chip SRAM size details.
Functional Description
Kinetis KE1xF Sub-Family Reference Manual, Rev. 4, 06/2019
334 NXP Semiconductors