NXP Semiconductors KE1xF Series, Reference Manual, Page: 310 / 1483

13.3 SRAM memory
13.3.1 SRAM sizes
This device contains SRAM tightly coupled to the ARM Cortex-M4 core. The on-chip
SRAM is split into SRAM_L and SRAM_U regions where the SRAM_L and SRAM_U
ranges form a contiguous block in the memory map anchored at address 0x2000_0000.
As such:
• SRAM_L is anchored to 0x1FFF_FFFF and occupies the space before this ending
address.
• SRAM_U is anchored to 0x2000_0000 and occupies the space after this beginning
address.
NOTE
Misaligned accesses across the 0x2000_0000 boundary are not
supported in the ARM Cortex-M4 architecture.
NOTE
Burst-access cannot occur across the 0x2000_0000 boundary
that separates the two SRAM arrays. The two arrays should be
treated as separate memory ranges for burst accesses.
The amount of SRAM for the devices covered in this document is shown in the following
table.
Device SRAM_L size
(KB)
SRAM_U size
(KB)
Total SRAM (KB) Address Range
MKE1xF512VLL15 32 32 64 0x1FFF_8000-0x2000_7FFF
MKE1xF512VLH15 32 32 64 0x1FFF_8000-0x2000_7FFF
MKE1xF256VLL15 16 16 32 0x1FFF_C000-0x2000_3FFF
MKE1xF256VLH15 16 16 32 0x1FFF_C000-0x2000_3FFF
13.3.2 SRAM retention in low power modes
The SRAM is retained power on to all power modes on this device.
SRAM memory
Kinetis KE1xF Sub-Family Reference Manual, Rev. 4, 06/2019
310 NXP Semiconductors