NXP Semiconductors KE1xF Series, Reference Manual, Page: 258 / 1483

DMA_INT field descriptions (continued)
Field Description
3
INT3
Interrupt Request 3
0 The interrupt request for corresponding channel is cleared
1 The interrupt request for corresponding channel is active
2
INT2
Interrupt Request 2
0 The interrupt request for corresponding channel is cleared
1 The interrupt request for corresponding channel is active
1
INT1
Interrupt Request 1
0 The interrupt request for corresponding channel is cleared
1 The interrupt request for corresponding channel is active
0
INT0
Interrupt Request 0
0 The interrupt request for corresponding channel is cleared
1 The interrupt request for corresponding channel is active
12.3.18 Error Register (DMA_ERR)
The ERR provides a bit map for the 16 channels, signaling the presence of an error for
each channel. The eDMA engine signals the occurrence of an error condition by setting
the appropriate bit in this register. The outputs of this register are enabled by the contents
of the EEI, and then routed to the interrupt controller. During the execution of the
interrupt-service routine associated with any DMA errors, it is software’s responsibility
to clear the appropriate bit, negating the error-interrupt request. Typically, a write to the
CERR in the interrupt-service routine is used for this purpose. The normal DMA channel
completion indicators (setting the transfer control descriptor DONE flag and the possible
assertion of an interrupt request) are not affected when an error is detected.
The contents of this register can also be polled because a non-zero value indicates the
presence of a channel error regardless of the state of the EEI. The state of any given
channel’s error indicators is affected by writes to this register; it is also affected by writes
to the CERR. On writes to the ERR, a one in any bit position clears the corresponding
channel’s error status. A zero in any bit position has no affect on the corresponding
channel’s current error status. The CERR is provided so the error indicator for a single
channel can easily be cleared.
Memory map/register definition
Kinetis KE1xF Sub-Family Reference Manual, Rev. 4, 06/2019
258 NXP Semiconductors