NXP Semiconductors KE1xF Series, Reference Manual, Page: 195 / 1483

Field Function
—
23
—
This read-only bit field is reserved and always has the value 0.
22-16
—
This read-only bit field is reserved and always has the value 0.
15
—
This read-only bit field is reserved and always has the value 0.
14-8
—
This read-only bit field is reserved and always has the value 0.
7
—
This read-only bit field is reserved and always has the value 0.
6-0
SEL0
Trigger MUX Input 0 Source Select
This read/write bit field is used to configure the MUX select for peripheral trigger input 0. Refer to the
Select Bit Fields table in the Features section for bit field information.
10.4.1.25 TRGMUX LPSPI0 (TRGMUX_LPSPI0)
10.4.1.25.1 Address
Register Offset
TRGMUX_LPSPI0 4006205Ch
TRGMUX Register
10.4.1.25.2 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R LK
Reserved
Rese
rved
Reserved
W
Reset
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
Rese
rved
Reserved
Rese
rved
SEL0
W
Reset
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Chapter 10 Trigger MUX Control (TRGMUX)
Kinetis KE1xF Sub-Family Reference Manual, Rev. 4, 06/2019
NXP Semiconductors 195