NXP Semiconductors KE1xF Series, Reference Manual, Page: 1395 / 1483

CANx_MCR field descriptions (continued)
Field Description
NOTE: LPMACK will be asserted within 180 CAN bits from the low-power mode request by the CPU, and
negated within 2 CAN bits after the low-power mode request removal (see Protocol timing ).
0 FlexCAN is not in a low-power mode.
1 FlexCAN is in a low-power mode.
19
WAKSRC
Wake Up Source
This bit defines whether the integrated low-pass filter is applied to protect the Rx CAN input from spurious
wake up. This bit can be written only in Freeze mode because it is blocked by hardware in other modes.
0 FlexCAN uses the unfiltered Rx input to detect recessive to dominant edges on the CAN bus.
1 FlexCAN uses the filtered Rx input to detect recessive to dominant edges on the CAN bus.
18
Reserved
This field is reserved.
When writing to this field, always write the reset value.
17
SRXDIS
Self Reception Disable
This bit defines whether FlexCAN is allowed to receive frames transmitted by itself. If this bit is asserted,
frames transmitted by the module will not be stored in any MB, regardless if the MB is programmed with
an ID that matches the transmitted frame, and no interrupt flag or interrupt signal will be generated due to
the frame reception. This bit can be written only in Freeze mode because it is blocked by hardware in
other modes.
0 Self reception enabled.
1 Self reception disabled.
16
IRMQ
Individual Rx Masking And Queue Enable
This bit indicates whether Rx matching process will be based either on individual masking and queue or
on masking scheme with CAN_RXMGMASK, CAN_RX14MASK, CAN_RX15MASK and
CAN_RXFGMASK. This bit can be written in Freeze mode only because it is blocked by hardware in other
modes.
0 Individual Rx masking and queue feature are disabled. For backward compatibility with legacy
applications, the reading of C/S word locks the MB even if it is EMPTY.
1 Individual Rx masking and queue feature are enabled.
15
DMA
DMA Enable
The DMA Enable bit controls whether the DMA feature is enabled or not. The DMA feature can only be
used in Rx FIFO, consequently the bit CAN_MCR[RFEN] must be asserted. When DMA and RFEN are
set, the CAN_IFLAG1[BUF5I] generates the DMA request and no RX FIFO interrupt is generated. This bit
can be written in Freeze mode only as it is blocked by hardware in other modes.
0 DMA feature for RX FIFO disabled.
1 DMA feature for RX FIFO enabled.
14
Reserved
This field is reserved.
This read-only field is reserved and always has the value 0.
13
LPRIOEN
Local Priority Enable
This bit is provided for backwards compatibility with legacy applications. It controls whether the local
priority feature is enabled or not. It is used to expand the ID used during the arbitration process. With this
expanded ID concept, the arbitration process is done based on the full 32-bit word, but the actual
transmitted ID still has 11-bit for standard frames and 29-bit for extended frames. This bit can be written
only in Freeze mode because it is blocked by hardware in other modes.
Table continues on the next page...
Chapter 50 CAN (FlexCAN)
Kinetis KE1xF Sub-Family Reference Manual, Rev. 4, 06/2019
NXP Semiconductors 1395