NXP Semiconductors KE1xF Series, Reference Manual, Page: 1393 / 1483

CANx_MCR field descriptions (continued)
Field Description
0 Not enabled to enter Freeze mode.
1 Enabled to enter Freeze mode.
29
RFEN
Rx FIFO Enable
This bit controls whether the Rx FIFO feature is enabled or not. When RFEN is set, MBs 0 to 5 cannot be
used for normal reception and transmission because the corresponding memory region (0x80-0xDC) is
used by the FIFO engine as well as additional MBs (up to 32, depending on CAN_CTRL2[RFFN] setting)
which are used as Rx FIFO ID Filter Table elements. RFEN also impacts the definition of the minimum
number of peripheral clocks per CAN bit as described in the table "Minimum Ratio Between Peripheral
Clock Frequency and CAN Bit Rate" (see
Arbitration and matching timing ). This bit can be written in
Freeze mode only because it is blocked by hardware in other modes.
0 Rx FIFO not enabled.
1 Rx FIFO enabled.
28
HALT
Halt FlexCAN
Assertion of this bit puts the FlexCAN module into Freeze mode. The CPU should clear it after initializing
the Message Buffers and the Control Registers CAN_CTRL1 and CAN_CTRL2. No reception or
transmission is performed by FlexCAN before this bit is cleared. Freeze mode cannot be entered while
FlexCAN is in a low power mode.
0 No Freeze mode request.
1 Enters Freeze mode if the FRZ bit is asserted.
27
NOTRDY
FlexCAN Not Ready
This read-only bit indicates that FlexCAN is either in Disable mode, Stop mode or Freeze mode. It is
negated once FlexCAN has exited these modes. This bit is not affected by soft reset.
0 FlexCAN module is either in Normal mode, Listen-Only mode or Loop-Back mode.
1 FlexCAN module is either in Disable mode, Stop mode or Freeze mode.
26
WAKMSK
Wake Up Interrupt Mask
This bit enables the Wake Up Interrupt generation under Self Wake Up mechanism.
0 Wake Up Interrupt is disabled.
1 Wake Up Interrupt is enabled.
25
SOFTRST
Soft Reset
When this bit is asserted, FlexCAN resets its internal state machines and some of the memory mapped
registers.
The SOFTRST bit can be asserted directly by the CPU when it writes to the MCR Register. Because soft
reset is synchronous and has to follow a request/acknowledge procedure across clock domains, it may
take some time to fully propagate its effect. The SOFTRST bit remains asserted while reset is pending,
and is automatically negated when reset completes. Therefore, software can poll this bit to know when the
soft reset has completed.
Soft reset cannot be applied while clocks are shut down in a low power mode. The module should be first
removed from low power mode, and then soft reset can be applied. This bit is not affected by soft reset.
0 No reset request.
1 Resets the registers affected by soft reset.
24
FRZACK
Freeze Mode Acknowledge
Table continues on the next page...
Chapter 50 CAN (FlexCAN)
Kinetis KE1xF Sub-Family Reference Manual, Rev. 4, 06/2019
NXP Semiconductors 1393